165 lines
3.6 KiB
ArmAsm
165 lines
3.6 KiB
ArmAsm
/*
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* Copyright (c) 2019 Synopsys.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Thread context switching
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*
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* This module implements the routines necessary for thread context switching
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* on ARCv2 CPUs.
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*
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* See isr_wrapper.S for details.
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*/
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <v2/irq.h>
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#include <swap_macros.h>
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GTEXT(arch_switch)
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/**
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*
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* @brief Initiate a cooperative context switch
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*
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* The arch_switch routine is invoked by various kernel services to effect
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* a cooperative context switch. Prior to invoking arch_switch, the caller
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* disables interrupts via irq_lock()
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* Given that arch_switch() is called to effect a cooperative context switch,
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* the caller-saved integer registers are saved on the stack by the function
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* call preamble to arch_switch. This creates a custom stack frame that will
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* be popped when returning from arch_switch, but is not suitable for handling
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* a return from an exception. Thus, the fact that the thread is pending because
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* of a cooperative call to arch_switch() has to be recorded via the
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* _CAUSE_COOP code in the relinquish_cause of the thread's k_thread structure.
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* The _rirq_exit()/_firq_exit() code will take care of doing the right thing
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* to restore the thread status.
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*
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* When arch_switch() is invoked, we know the decision to perform a context
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* switch or not has already been taken and a context switch must happen.
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*
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*
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* C function prototype:
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*
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* void arch_switch(void *switch_to, void **switched_from);
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*
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*/
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SECTION_FUNC(TEXT, arch_switch)
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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push_s r0
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push_s r1
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push_s blink
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bl read_timer_start_of_swap
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pop_s blink
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pop_s r1
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pop_s r0
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#endif
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/*
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* r0 = new_thread->switch_handle = switch_to thread,
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* r1 = &old_thread->switch_handle
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* get old_thread from r1
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*/
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sub r2, r1, ___thread_t_switch_handle_OFFSET
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st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
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/*
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* Save status32 and blink on the stack before the callee-saved registers.
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* This is the same layout as the start of an IRQ stack frame.
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*/
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lr r3, [_ARC_V2_STATUS32]
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push_s r3
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#ifdef CONFIG_ARC_HAS_SECURE
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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lr r3, [_ARC_V2_SEC_STAT]
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#else
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mov_s r3, 0
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#endif
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push_s r3
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#endif
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push_s blink
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_store_old_thread_callee_regs
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/* disable stack checking here, as sp will be changed to target
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* thread'sp
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*/
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_disable_stack_checking r3
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mov_s r2, r0
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_load_new_thread_callee_regs
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breq r3, _CAUSE_RIRQ, _switch_return_from_rirq
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nop_s
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breq r3, _CAUSE_FIRQ, _switch_return_from_firq
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nop_s
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/* fall through to _switch_return_from_coop */
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.balign 4
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_switch_return_from_coop:
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pop_s blink /* pc into blink */
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#ifdef CONFIG_ARC_HAS_SECURE
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pop_s r3 /* pop SEC_STAT */
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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sflag r3
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#endif
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#endif
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pop_s r3 /* status32 into r3 */
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kflag r3 /* write status32 */
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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push_s blink
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bl read_timer_end_of_swap
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pop_s blink
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#endif /* CONFIG_EXECUTION_BENCHMARKING */
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j_s [blink]
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.balign 4
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_switch_return_from_rirq:
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_switch_return_from_firq:
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_set_misc_regs_irq_switch_from_irq
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/* use lowest interrupt priority to simulate
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* a interrupt return to load left regs of new
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* thread
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*/
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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or r3, r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
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#else
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or r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
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#endif
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#ifdef CONFIG_ARC_NORMAL_FIRMWARE
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mov_s r0, _ARC_V2_AUX_IRQ_ACT
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mov_s r1, r3
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mov_s r6, ARC_S_CALL_AUX_WRITE
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sjli SJLI_CALL_ARC_SECURE
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#else
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sr r3, [_ARC_V2_AUX_IRQ_ACT]
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#endif
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rtie
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