268 lines
6.8 KiB
ArmAsm
268 lines
6.8 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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* Copyright (c) 2018 Synopsys.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Fault handlers for ARCv2
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*
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* Fault handlers for ARCv2 processors.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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#include <syscall.h>
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GTEXT(_Fault)
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GTEXT(__reset)
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GTEXT(__memory_error)
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GTEXT(__instruction_error)
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GTEXT(__ev_machine_check)
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GTEXT(__ev_tlb_miss_i)
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GTEXT(__ev_tlb_miss_d)
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GTEXT(__ev_prot_v)
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GTEXT(__ev_privilege_v)
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GTEXT(__ev_swi)
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GTEXT(__ev_trap)
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GTEXT(__ev_extension)
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GTEXT(__ev_div_zero)
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GTEXT(__ev_dc_error)
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GTEXT(__ev_maligned)
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(z_irq_do_offload);
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#endif
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.macro _save_exc_regs_into_stack
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#ifdef CONFIG_ARC_HAS_SECURE
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/* ERSEC_STAT is IOW/RAZ in normal mode */
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lr r0,[_ARC_V2_ERSEC_STAT]
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st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
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#endif
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lr r0,[_ARC_V2_ERET]
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st_s r0, [sp, ___isf_t_pc_OFFSET]
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lr r0,[_ARC_V2_ERSTATUS]
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st_s r0, [sp, ___isf_t_status32_OFFSET]
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.endm
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/*
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* The exception handling will use top part of interrupt stack to
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* get smaller memory footprint, because exception is not frequent.
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* To reduce the impact on interrupt handling, especially nested interrupt
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* the top part of interrupt stack cannot be too large, so add a check
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* here
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*/
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#if CONFIG_ARC_EXCEPTION_STACK_SIZE > (CONFIG_ISR_STACK_SIZE >> 1)
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#error "interrupt stack size is too small"
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#endif
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/*
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* @brief Fault handler installed in the fault and reserved vectors
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__memory_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__instruction_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_machine_check)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_i)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_div_zero)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_dc_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
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_exc_entry:
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/*
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* re-use the top part of interrupt stack as exception
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* stack. If this top part is used by interrupt handling,
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* and exception is raised, then here it's guaranteed that
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* exception handling has necessary stack to use
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*/
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mov_s ilink, sp
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_get_curr_cpu_irq_stack sp
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sub sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
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/*
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* save caller saved registers
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* this stack frame is set up in exception stack,
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* not in the original sp (thread stack or interrupt stack).
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* Because the exception may be raised by stack checking or
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* mpu protect violation related to stack. If this stack frame
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* is setup in original sp, double exception may be raised during
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* _create_irq_stack_frame, which is unrecoverable.
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*/
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_create_irq_stack_frame
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_save_exc_regs_into_stack
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/* sp is parameter of _Fault */
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mov_s r0, sp
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/* ilink is the thread's original sp */
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mov_s r1, ilink
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jl _Fault
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_exc_return:
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/* the exception cause must be fixed in exception handler when exception returns
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* directly, or exception will be repeated.
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*
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* If thread switch is raised in exception handler, the context of old thread will
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* not be saved, i.e., it cannot be recovered, because we don't know where the
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* exception comes out, thread context?irq_context?nest irq context?
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*/
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_get_next_switch_handle
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breq r0, r2, _exc_return_from_exc
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mov_s r2, r0
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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/*
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* sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
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* use a fake interrupt return to simulate an exception turn.
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* ERM and IRM record which mode the cpu should return, 1: secure
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* 0: normal
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*/
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lr r3,[_ARC_V2_ERSEC_STAT]
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btst r3, 31
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bset.nz r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
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bclr.z r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
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sflag r3
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#endif
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/* clear AE bit to forget this was an exception, and go to
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* register bank0 (if exception is raised in firq with 2 reg
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* banks, then we may be bank1)
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*/
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#if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
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/* save r2 in ilink because of the possible following reg
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* bank switch
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*/
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mov_s ilink, r2
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#endif
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lr r3, [_ARC_V2_STATUS32]
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and r3,r3,(~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
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kflag r3
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/* pretend lowest priority interrupt happened to use common handler
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* if exception is raised in irq, i.e., _ARC_V2_AUX_IRQ_ACT !=0,
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* ignore irq handling, we cannot return to irq handling which may
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* raise exception again. The ignored interrupts will be re-triggered
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* if not cleared, or re-triggered by interrupt sources, or just missed
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*/
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
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#else
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mov_s r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
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#endif
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#ifdef CONFIG_ARC_NORMAL_FIRMWARE
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push_s r2
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mov_s r0, _ARC_V2_AUX_IRQ_ACT
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mov_s r1, r3
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mov_s r6, ARC_S_CALL_AUX_WRITE
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sjli SJLI_CALL_ARC_SECURE
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pop_s r2
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#else
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sr r3, [_ARC_V2_AUX_IRQ_ACT]
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#endif
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#if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
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mov r2, ilink
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#endif
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/* Assumption: r2 has next thread */
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b _rirq_newthread_switch
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_exc_return_from_exc:
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/* exception handler may change return address.
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* reload it
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*/
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ld_s r0, [sp, ___isf_t_pc_OFFSET]
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sr r0, [_ARC_V2_ERET]
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_pop_irq_stack_frame
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mov_s sp, ilink
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rtie
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/* separated entry for trap which may be used by irq_offload, USERPSACE */
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
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/* get the id of trap_s */
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lr ilink, [_ARC_V2_ECR]
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and ilink, ilink, 0x3f
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#ifdef CONFIG_USERSPACE
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cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
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bne _do_non_syscall_trap
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/* do sys_call */
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mov_s ilink, K_SYSCALL_LIMIT
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cmp r6, ilink
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blo valid_syscall_id
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mov_s r0, r6
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mov_s r6, K_SYSCALL_BAD
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valid_syscall_id:
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/* create a sys call frame
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* caller regs (r0 - 12) are saved in _create_irq_stack_frame
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* ok to use them later
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*/
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_create_irq_stack_frame
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_save_exc_regs_into_stack
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/* exc return and do sys call in kernel mode,
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* so need to clear U bit, r0 is already loaded
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* with ERSTATUS in _save_exc_regs_into_stack
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*/
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bclr r0, r0, _ARC_V2_STATUS32_U_BIT
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sr r0, [_ARC_V2_ERSTATUS]
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mov_s r0, _arc_do_syscall
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sr r0, [_ARC_V2_ERET]
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rtie
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_do_non_syscall_trap:
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#endif /* CONFIG_USERSPACE */
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#ifdef CONFIG_IRQ_OFFLOAD
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/*
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* IRQ_OFFLOAD is to simulate interrupt handling through exception,
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* so its entry is different with normal exception handling, it is
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* handled in isr stack
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*/
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cmp ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
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bne _exc_entry
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/* save caller saved registers */
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_create_irq_stack_frame
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_save_exc_regs_into_stack
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/* check whether irq stack is used */
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_check_and_inc_int_nest_counter r0, r1
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bne.d exc_nest_handle
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mov_s r0, sp
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_get_curr_cpu_irq_stack sp
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exc_nest_handle:
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push_s r0
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jl z_irq_do_offload
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pop sp
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_dec_int_nest_counter r0, r1
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_pop_irq_stack_frame
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/* ERSTATUS, ERET are not changed, so ok to rtie */
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rtie
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#endif /* CONFIG_IRQ_OFFLOAD */
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b _exc_entry
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