291 lines
7.0 KiB
ArmAsm
291 lines
7.0 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Handling of transitions to-and-from fast IRQs (FIRQ)
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*
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* This module implements the code for handling entry to and exit from Fast IRQs.
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*
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* See isr_wrapper.S for details.
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*/
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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GTEXT(_firq_enter)
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GTEXT(_firq_exit)
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/**
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*
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* @brief Work to be done before handing control to a FIRQ ISR
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*
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* The processor switches to a second register bank so registers from the
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* current bank do not have to be preserved yet. The only issue is the LP_START/
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* LP_COUNT/LP_END registers, which are not banked. These can be saved
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* in available callee saved registers.
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*
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* If all FIRQ ISRs are programmed such that there are no use of the LP
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* registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
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* not set, then the kernel can be configured to not save and restore them.
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*
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* When entering a FIRQ, interrupts might as well be locked: the processor is
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* running at its highest priority, and cannot be interrupted by any other
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* interrupt. An exception, however, can be taken.
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*
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* Assumption by _isr_demux: r3 is untouched by _firq_enter.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_enter)
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/*
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* ATTENTION:
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* If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
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* not need to be saved.
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* If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
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* This has already been done by _isr_wrapper.
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*/
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#ifdef CONFIG_ARC_STACK_CHECKING
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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lr r2, [_ARC_V2_SEC_STAT]
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bclr r2, r2, _ARC_V2_SEC_STAT_SSC_BIT
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sflag r2
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#else
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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#endif
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#endif
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#if CONFIG_RGF_NUM_BANKS != 1
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/*
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* Save LP_START/LP_COUNT/LP_END because called handler might use.
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* Save these in callee saved registers to avoid using memory.
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* These will be saved by the compiler if it needs to spill them.
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*/
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mov r23,lp_count
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lr r24, [_ARC_V2_LP_START]
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lr r25, [_ARC_V2_LP_END]
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#endif
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/* check whether irq stack is used */
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_check_and_inc_int_nest_counter r0, r1
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bne.d firq_nest
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mov_s r0, sp
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_get_curr_cpu_irq_stack sp
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#if CONFIG_RGF_NUM_BANKS != 1
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b firq_nest_1
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firq_nest:
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/*
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* because firq and rirq share the same interrupt stack,
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* switch back to original register bank to get correct sp.
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* to get better firq latency, an approach is to prepare
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* separate interrupt stack for firq and do not do thread
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* switch in firq.
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*/
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lr r1, [_ARC_V2_STATUS32]
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and r1, r1, ~_ARC_V2_STATUS32_RB(7)
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kflag r1
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/* here use _ARC_V2_USER_SP and ilink to exchange sp
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* save original value of _ARC_V2_USER_SP and ilink into
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* the stack of interrupted context first, then restore them later
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*/
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push ilink
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PUSHAX ilink, _ARC_V2_USER_SP
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/* sp here is the sp of interrupted context */
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sr sp, [_ARC_V2_USER_SP]
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/* here, bank 0 sp must go back to the value before push and
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* PUSHAX as we will switch to bank1, the pop and POPAX later will
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* change bank1's sp, not bank0's sp
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*/
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add sp, sp, 8
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/* switch back to banked reg, only ilink can be used */
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lr ilink, [_ARC_V2_STATUS32]
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or ilink, ilink, _ARC_V2_STATUS32_RB(1)
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kflag ilink
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lr sp, [_ARC_V2_USER_SP]
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POPAX ilink, _ARC_V2_USER_SP
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pop ilink
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firq_nest_1:
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#else
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firq_nest:
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#endif
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push_s r0
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j @_isr_demux
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/**
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*
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* @brief Work to be done exiting a FIRQ
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_exit)
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#if CONFIG_RGF_NUM_BANKS != 1
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/* restore lp_count, lp_start, lp_end from r23-r25 */
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mov lp_count,r23
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sr r24, [_ARC_V2_LP_START]
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sr r25, [_ARC_V2_LP_END]
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#endif
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_dec_int_nest_counter r0, r1
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_check_nest_int_by_irq_act r0, r1
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jne _firq_no_switch
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/* sp is struct k_thread **old of z_arc_switch_in_isr
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* which is a wrapper of z_get_next_switch_handle.
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* r0 contains the 1st thread in ready queue. if
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* it equals _current(r2) ,then do swap, or no swap.
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*/
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_get_next_switch_handle
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/* restore interrupted context' sp */
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pop sp
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cmp r0, r2
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bne _firq_switch
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/* fall to no switch */
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.balign 4
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_firq_no_switch:
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/*
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* Keeping this code block close to those that use it allows using brxx
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* instruction instead of a pair of cmp and bxx
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*/
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#if CONFIG_RGF_NUM_BANKS == 1
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_pop_irq_stack_frame
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#endif
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rtie
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.balign 4
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_firq_switch:
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#if CONFIG_RGF_NUM_BANKS != 1
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/*
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* save r0, r2 in irq stack for a while, as they will be changed by register
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* bank switch
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*/
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_get_curr_cpu_irq_stack r1
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st r0, [r1, -4]
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st r2, [r1, -8]
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/*
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* We know there is no interrupted interrupt of lower priority at this
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* point, so when switching back to register bank 0, it will contain the
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* registers from the interrupted thread.
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*/
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#if defined(CONFIG_USERSPACE)
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/* when USERSPACE is configured, here need to consider the case where firq comes
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* out in user mode, according to ARCv2 ISA and nsim, the following micro ops
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* will be executed:
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* sp<-reg bank1'sp
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* switch between sp and _ARC_V2_USER_SP
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* then:
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* sp is the sp of kernel stack of interrupted thread
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* _ARC_V2_USER_SP is reg bank1'sp
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* the sp of user stack of interrupted thread is reg bank0'sp
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* if firq comes out in kernel mode, the following micro ops will be executed:
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* sp<-reg bank'sp
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* so, sw needs to do necessary handling to set up the correct sp
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*/
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lr r0, [_ARC_V2_AUX_IRQ_ACT]
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bbit0 r0, 31, _firq_from_kernel
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aex sp, [_ARC_V2_USER_SP]
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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aex sp, [_ARC_V2_USER_SP]
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b _firq_create_irq_stack_frame
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_firq_from_kernel:
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#endif
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/* chose register bank #0 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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_firq_create_irq_stack_frame:
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/* we're back on the outgoing thread's stack */
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_create_irq_stack_frame
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/*
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* In a FIRQ, STATUS32 of the outgoing thread is in STATUS32_P0 and the
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* PC in ILINK: save them in status32/pc respectively.
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*/
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lr r0, [_ARC_V2_STATUS32_P0]
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st_s r0, [sp, ___isf_t_status32_OFFSET]
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st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
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/*
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* load r0, r2 from irq stack
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*/
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_get_curr_cpu_irq_stack r1
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ld r0, [r1, -4]
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ld r2, [r1, -8]
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#endif
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/* r2 is old thread */
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_irq_store_old_thread_callee_regs
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st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
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/* mov new thread (r0) to r2 */
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mov r2, r0
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_load_new_thread_callee_regs
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breq r3, _CAUSE_RIRQ, _firq_switch_from_rirq
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nop_s
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breq r3, _CAUSE_FIRQ, _firq_switch_from_firq
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nop_s
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/* fall through */
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.balign 4
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_firq_switch_from_coop:
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_set_misc_regs_irq_switch_from_coop
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/* pc into ilink */
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pop_s r0
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mov_s ilink, r0
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pop_s r0 /* status32 into r0 */
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sr r0, [_ARC_V2_STATUS32_P0]
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rtie
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.balign 4
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_firq_switch_from_rirq:
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_firq_switch_from_firq:
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_set_misc_regs_irq_switch_from_irq
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_pop_irq_stack_frame
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ld ilink, [sp, -4] /* status32 into ilink */
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sr ilink, [_ARC_V2_STATUS32_P0]
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ld ilink, [sp, -8] /* pc into ilink */
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/* LP registers are already restored, just switch back to bank 0 */
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rtie
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