80 lines
2.9 KiB
YAML
80 lines
2.9 KiB
YAML
# Copyright (c) 2018 Foundries.io
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# Copyright (c) 2020 ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Cypress Interrupt Multiplex
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The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
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user can select up to 32 interrupts sources from the 240 possible vectors
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to be processed in the Cortex-M0+ CPU.
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At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
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configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
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4 interrupt sources by grouping intmux channels. These means that each byte
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from intmux[0~7] store a 'vector number' which selects the peripheral
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interrupt source in the multiplexer. The multiplexer is placed before
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Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
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directly connected to NVIC and doesn't require any special configuration.
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On a general view, the below represents the Interrupt Multiplexer
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configuration and how the Cortex-M0+ NVIC sources are organized. Each
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channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
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The vector number selects the PSoC-6 peripheral interrupt source for the
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Cortex-M0+ NVIC controller line.
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intmux[0] = {ch03, ch02, ch01, ch00}
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intmux[1] = {ch07, ch06, ch05, ch04}
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...
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intmux[7] = {ch31, ch30, ch29, ch28}
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In pratical terms, the Cortex-M0+ requires user to define all NVIC interrupt
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sources and the proper NVIC interrupt order. With that, the system configures
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the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
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More information about it at PSoC-6 Architecture Technical Reference Manual,
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section CPU Sub System (CPUSS) Registers.
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The below fragment configure the GPIO Port 0 to generate an interrupt at
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Cortex-M0+ NVIC:
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At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:
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gpio_prt0: gpio@40320100 {
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interrupts = <2 1>;
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};
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In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
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must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
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This can be defined at <board>_m0.dts file:
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&gpio_prt0 {
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interrupt-parent = <&intmux_ch20>;
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};
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The translation of these two definitions is:
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CH REGS INT NUM CH CH/REG
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intmux[20 mod 8] |= 0x02 << (20 mod 4);
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These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
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The interrupt can be enabled/disable at NVIC at line 20 as usual.
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Notes:
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1) Multiple definitions will generate multiple interrutps
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2) The interrupt sources are shared between Cortex-M0+/M4. These means, can
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trigger action in parallel in both processors.
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3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
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at interrupt-parent properties.
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4) Only the peripherals used by Cortex-M0+ should be configured.
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compatible: "cypress,psoc6-intmux"
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include: base.yaml
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properties:
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reg:
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required: true
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label:
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required: true
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