84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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static int mimxrt1015_evk_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay)
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart4), okay)
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/* LPUART4 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_LPUART4_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_LPUART4_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_LPUART4_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_33_LPUART4_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay)
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/* LPI2C1 SCL, SDA */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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return 0;
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}
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SYS_INIT(mimxrt1015_evk_init, PRE_KERNEL_1, 0);
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