zephyr/boards/beagle/beaglev_fire
Alex Charlton efc2cfe326 boards: beaglev_fire: fix memory address
Per the docs, the memory at address 0x80000000 ends at 0xC0000000.
In other words, the address space is 0x40000000, which is only half
of the size we want to map. This means that the upper address space
previously mapped was overlapping with the space reserved for non-cached
memory.

Instead, we map the entire 2GB at 0x1000000000, which is the correct
address for cached DDR that occupies more than 1 GB.

We defined a new node in the device tree for this memory region,
`beaglev.ddr_cached_high`. We did not reuse the `soc` node because
we needed to redefine the `#address-cells` to be 2, and doing so
would have affected other nodes under `soc`.

Signed-off-by: Alex Charlton <alex.n.charlton@gmail.com>
2024-11-27 08:14:49 +01:00
..
doc boards: beaglev_fire: fix memory address 2024-11-27 08:14:49 +01:00
Kconfig.beaglev_fire soc: polarfire: split into cpu clusters 2024-08-28 06:50:40 -04:00
beaglev_fire_common.dtsi boards: beaglev_fire: fix memory address 2024-11-27 08:14:49 +01:00
beaglev_fire_defconfig soc: polarfire: split into cpu clusters 2024-08-28 06:50:40 -04:00
beaglev_fire_polarfire_e51.dts boards: beaglev_fire: fix uart 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_e51.yaml boards: beaglev_fire: fix memory address 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_e51_defconfig
beaglev_fire_polarfire_u54.dts boards: beaglev_fire: fix uart 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_u54.yaml boards: beaglev_fire: fix memory address 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_u54_defconfig
beaglev_fire_polarfire_u54_smp.dts boards: beaglev_fire: fix uart 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_u54_smp.yaml boards: beaglev_fire: fix memory address 2024-11-27 08:14:49 +01:00
beaglev_fire_polarfire_u54_smp_defconfig
board.yml