198 lines
5.2 KiB
C
198 lines
5.2 KiB
C
/*
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* Copyright (c) 2018 Foundries.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief RV32M1 INTMUX (interrupt multiplexer) driver
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*
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* This driver provides support for level 2 interrupts on the RV32M1
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* SoC using the INTMUX peripheral.
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*
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* Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
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* INTMUX0 is wired to the RI5CY event unit interrupt table, while
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* INTMUX1 is used with ZERO-RISCY.
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*
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* For this reason, only a single intmux device is declared here. The
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* dtsi for each core needs to set up the intmux device and any
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* associated IRQ numbers to work with this driver.
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*/
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#include <kernel.h>
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#include <clock_control.h>
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#include <init.h>
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#include <irq.h>
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#include <irq_nextlevel.h>
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#include <sw_isr_table.h>
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#include <soc.h>
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#include <dt-bindings/interrupt-controller/openisa-intmux.h>
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/*
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* CHn_VEC registers are offset by a value that is convenient if
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* you're dealing with a Cortex-M NVIC vector table; we're not, so it
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* needs to be subtracted out to get a useful value.
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*/
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#define VECN_OFFSET 48U
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struct rv32m1_intmux_config {
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INTMUX_Type *regs;
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char *clock_name;
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clock_control_subsys_t clock_subsys;
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struct _isr_table_entry *isr_base;
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};
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#define DEV_CFG(dev) \
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((struct rv32m1_intmux_config *)(dev->config->config_info))
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#define DEV_REGS(dev) (DEV_CFG(dev)->regs)
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DEVICE_DECLARE(intmux);
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/*
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* <irq_nextlevel.h> API
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*/
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static void rv32m1_intmux_irq_enable(struct device *dev, u32_t irq)
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{
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INTMUX_Type *regs = DEV_REGS(dev);
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u32_t channel = rv32m1_intmux_channel(irq);
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u32_t line = rv32m1_intmux_line(irq);
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regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line);
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}
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static void rv32m1_intmux_irq_disable(struct device *dev, u32_t irq)
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{
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INTMUX_Type *regs = DEV_REGS(dev);
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u32_t channel = rv32m1_intmux_channel(irq);
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u32_t line = rv32m1_intmux_line(irq);
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regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line);
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}
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static u32_t rv32m1_intmux_get_state(struct device *dev)
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{
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INTMUX_Type *regs = DEV_REGS(dev);
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size_t i;
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for (i = 0; i < INTMUX_CHn_IER_31_0_COUNT; i++) {
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if (regs->CHANNEL[i].CHn_IER_31_0) {
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return 1;
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}
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}
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return 0;
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}
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/*
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* IRQ handling.
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*/
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#define ISR_ENTRY(channel, line) \
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((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
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static void rv32m1_intmux_isr(void *arg)
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{
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struct device *dev = DEVICE_GET(intmux);
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INTMUX_Type *regs = DEV_REGS(dev);
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u32_t channel = POINTER_TO_UINT(arg);
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u32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2) - VECN_OFFSET;
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struct _isr_table_entry *isr_base = DEV_CFG(dev)->isr_base;
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struct _isr_table_entry *entry = &isr_base[ISR_ENTRY(channel, line)];
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entry->isr(entry->arg);
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}
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/*
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* Instance and initialization
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*/
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static const struct irq_next_level_api rv32m1_intmux_apis = {
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.intr_enable = rv32m1_intmux_irq_enable,
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.intr_disable = rv32m1_intmux_irq_disable,
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.intr_get_state = rv32m1_intmux_get_state,
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};
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static const struct rv32m1_intmux_config rv32m1_intmux_cfg = {
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.regs = (INTMUX_Type *)DT_OPENISA_RV32M1_INTMUX_INTMUX_BASE_ADDRESS,
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.clock_name = DT_OPENISA_RV32M1_INTMUX_INTMUX_CLOCK_CONTROLLER,
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.clock_subsys =
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UINT_TO_POINTER(DT_OPENISA_RV32M1_INTMUX_INTMUX_CLOCK_NAME),
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.isr_base = &_sw_isr_table[CONFIG_2ND_LVL_ISR_TBL_OFFSET],
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};
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static int rv32m1_intmux_init(struct device *dev)
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{
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const struct rv32m1_intmux_config *config = DEV_CFG(dev);
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INTMUX_Type *regs = DEV_REGS(dev);
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struct device *clock_dev = device_get_binding(config->clock_name);
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size_t i;
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if (!clock_dev) {
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return -ENODEV;
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}
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/* Enable INTMUX clock. */
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clock_control_on(clock_dev, config->clock_subsys);
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/*
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* Reset all channels, not just the ones we're configured to
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* support. We don't want to continue to take level 2 IRQs
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* enabled by bootloaders, for example.
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*/
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for (i = 0; i < INTMUX_CHn_CSR_COUNT; i++) {
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regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
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}
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/* Connect and enable level 1 (channel) interrupts. */
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_0
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IRQ_CONNECT(INTMUX_CH0_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(0), 0);
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irq_enable(INTMUX_CH0_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_1
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IRQ_CONNECT(INTMUX_CH1_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(1), 0);
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irq_enable(INTMUX_CH1_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_2
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IRQ_CONNECT(INTMUX_CH2_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(2), 0);
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irq_enable(INTMUX_CH2_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_3
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IRQ_CONNECT(INTMUX_CH3_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(3), 0);
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irq_enable(INTMUX_CH3_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_4
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IRQ_CONNECT(INTMUX_CH4_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(4), 0);
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irq_enable(INTMUX_CH4_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_5
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IRQ_CONNECT(INTMUX_CH5_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(5), 0);
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irq_enable(INTMUX_CH5_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_6
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IRQ_CONNECT(INTMUX_CH6_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(6), 0);
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irq_enable(INTMUX_CH6_IRQ);
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#endif
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_7
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IRQ_CONNECT(INTMUX_CH7_IRQ, 0, rv32m1_intmux_isr,
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UINT_TO_POINTER(7), 0);
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irq_enable(INTMUX_CH7_IRQ);
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#endif
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return 0;
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}
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DEVICE_AND_API_INIT(intmux, DT_OPENISA_RV32M1_INTMUX_INTMUX_LABEL,
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&rv32m1_intmux_init, NULL,
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&rv32m1_intmux_cfg, PRE_KERNEL_1,
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CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis);
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