Francois Ramu 4d9dd59310 soc: arm: stm32wb has no PWR clock to enable ... The stm32wb soc does not have any PWR clock for its power IP block when initializing the module. Signed-off-by: Francois Ramu <francois.ramu@st.com>		2020-07-09 17:35:43 +02:00
..
common	drivers: STM32 dualcore concurrent register access protection with HSEM	2020-07-09 11:27:56 +02:00
stm32f0	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32f1	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32f2	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32f3	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32f4	drivers: pwm: stm32: refactor driver using LL API	2020-06-19 15:18:50 +02:00
stm32f7	soc: stm32: Add support for stm32f745xx	2020-06-23 19:05:26 +02:00
stm32g0	drivers: pwm: stm32: refactor driver using LL API	2020-06-19 15:18:50 +02:00
stm32g4	drivers: pwm: stm32: refactor driver using LL API	2020-06-19 15:18:50 +02:00
stm32h7	drivers: STM32 dualcore concurrent register access protection with HSEM	2020-07-09 11:27:56 +02:00
stm32l0	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32l1	soc: arm: st_stm32: add include of devictree.h in soc.h	2020-06-19 08:55:44 -05:00
stm32l4	drivers: pwm: stm32: refactor driver using LL API	2020-06-19 15:18:50 +02:00
stm32l5	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
stm32mp1	drivers: STM32 dualcore concurrent register access protection with HSEM	2020-07-09 11:27:56 +02:00
stm32wb	soc: arm: stm32wb has no PWR clock to enable	2020-07-09 17:35:43 +02:00
CMakeLists.txt	drivers: STM32 dualcore concurrent register access protection with HSEM	2020-07-09 11:27:56 +02:00
Kconfig	kconfig: Clean up header comments and make them consistent	2019-11-04 17:31:27 -05:00
Kconfig.defconfig	…
Kconfig.soc	kconfig: Clean up header comments and make them consistent	2019-11-04 17:31:27 -05:00