66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
/*
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* Copyright (c) 2020 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM MCU family devicetree helper macros
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*/
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#ifndef _ATMEL_SAM_DT_H_
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#define _ATMEL_SAM_DT_H_
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#include <devicetree.h>
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/* Devicetree related macros to construct pin mux config data */
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/* Get a node id from a pinctrl-0 prop at index 'i' */
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#define NODE_ID_FROM_PINCTRL_0(inst, i) \
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DT_INST_PHANDLE_BY_IDX(inst, pinctrl_0, i)
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/* Get PIN associated with pinctrl-0 pin at index 'i' */
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#define ATMEL_SAM_PIN(inst, i) \
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DT_PHA(NODE_ID_FROM_PINCTRL_0(inst, i), atmel_pins, pin)
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/* Get PIO register address associated with pinctrl-0 pin at index 'i' */
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#define ATMEL_SAM_PIN_TO_PIO_REG_ADDR(inst, i) \
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DT_REG_ADDR(DT_PHANDLE(NODE_ID_FROM_PINCTRL_0(inst, i), atmel_pins))
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/* Get peripheral id for PIO associated with pinctrl-0 pin at index 'i' */
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#define ATMEL_SAM_PIN_2_PIO_PERIPH_ID(inst, i) \
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DT_PROP_BY_PHANDLE(NODE_ID_FROM_PINCTRL_0(inst, i),\
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atmel_pins, peripheral_id)
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/* Get peripheral cfg associated wiith pinctrl-0 pin at index 'i' */
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#define ATMEL_SAM_PIN_PERIPH(inst, i) \
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DT_PHA(NODE_ID_FROM_PINCTRL_0(inst, i), atmel_pins, peripheral)
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/* Construct a soc_gpio_pin element for pin cfg */
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#define ATMEL_SAM_DT_PIN(inst, idx) \
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{ \
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1 << ATMEL_SAM_PIN(inst, idx), \
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(Pio *)ATMEL_SAM_PIN_TO_PIO_REG_ADDR(inst, idx),\
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ATMEL_SAM_PIN_2_PIO_PERIPH_ID(inst, idx), \
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ATMEL_SAM_PIN_PERIPH(inst, idx) << 16 \
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}
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/* Get the number of pins for pinctrl-0 */
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#define ATMEL_SAM_DT_NUM_PINS(inst) DT_INST_PROP_LEN(inst, pinctrl_0)
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/* internal macro to structure things for use with UTIL_LISTIFY */
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#define ATMEL_SAM_DT_PIN_ELEM(idx, inst) ATMEL_SAM_DT_PIN(inst, idx),
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/* Construct an array intializer for soc_gpio_pin for a device instance */
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#define ATMEL_SAM_DT_PINS(inst) \
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{ UTIL_LISTIFY(ATMEL_SAM_DT_NUM_PINS(inst), \
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ATMEL_SAM_DT_PIN_ELEM, inst) \
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}
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/* Devicetree macros related to clock */
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#define ATMEL_SAM_DT_CPU_CLK_FREQ_HZ \
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DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
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#endif /* _ATMEL_SAM_SOC_DT_H_ */
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