469 lines
13 KiB
C
469 lines
13 KiB
C
/*
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* Copyright (c) 2022 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <assert.h>
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#include <soc.h>
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#include <zephyr/sys/onoff.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
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#include <zephyr/logging/log.h>
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#include <da1469x_clock.h>
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LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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#define DT_DRV_COMPAT smartbond_clock
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struct lpc_clock_state {
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uint8_t rcx_started : 1;
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uint8_t rcx_ready : 1;
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uint8_t rc32k_started : 1;
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uint8_t rc32k_ready : 1;
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uint8_t xtal32k_started : 1;
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uint8_t xtal32k_ready : 1;
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uint32_t rcx_freq;
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uint32_t rc32k_freq;
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} lpc_clock_state = {
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.rcx_freq = DT_PROP(DT_NODELABEL(rcx), clock_frequency),
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.rc32k_freq = DT_PROP(DT_NODELABEL(rc32k), clock_frequency),
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};
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#define CALIBRATION_INTERVAL (DT_NODE_HAS_STATUS(DT_NODELABEL(rcx), okay) ? \
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DT_PROP(DT_NODELABEL(rcx), calibration_interval) : \
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DT_PROP(DT_NODELABEL(rc32k), calibration_interval))
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static void calibration_work_cb(struct k_work *work);
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static void xtal32k_settle_work_cb(struct k_work *work);
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static K_WORK_DELAYABLE_DEFINE(calibration_work, calibration_work_cb);
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static K_WORK_DELAYABLE_DEFINE(xtal32k_settle_work, xtal32k_settle_work_cb);
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static void calibration_work_cb(struct k_work *work)
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{
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if (lpc_clock_state.rcx_started) {
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da1469x_clock_lp_rcx_calibrate();
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lpc_clock_state.rcx_ready = true;
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lpc_clock_state.rcx_freq = da1469x_clock_lp_rcx_freq_get();
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k_work_schedule(&calibration_work,
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K_MSEC(1000 * CALIBRATION_INTERVAL));
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LOG_DBG("RCX calibration done, RCX freq: %d",
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(int)lpc_clock_state.rcx_freq);
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} else if (lpc_clock_state.rc32k_started) {
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da1469x_clock_lp_rc32k_calibrate();
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lpc_clock_state.rc32k_ready = true;
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lpc_clock_state.rc32k_freq = da1469x_clock_lp_rc32k_freq_get();
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k_work_schedule(&calibration_work,
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K_MSEC(1000 * CALIBRATION_INTERVAL));
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LOG_DBG("RC32K calibration done, RC32K freq: %d",
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(int)lpc_clock_state.rc32k_freq);
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}
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}
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static void xtal32k_settle_work_cb(struct k_work *work)
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{
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if (lpc_clock_state.xtal32k_started && !lpc_clock_state.xtal32k_ready) {
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LOG_DBG("XTAL32K settled.");
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lpc_clock_state.xtal32k_ready = true;
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}
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}
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static void smartbond_start_rc32k(void)
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{
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if ((CRG_TOP->CLK_RC32K_REG & CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk) == 0) {
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CRG_TOP->CLK_RC32K_REG |= CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk;
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lpc_clock_state.rc32k_started = true;
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}
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if (!lpc_clock_state.rc32k_ready && (CALIBRATION_INTERVAL > 0)) {
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if (!k_work_is_pending(&calibration_work.work)) {
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k_work_schedule(&calibration_work,
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K_MSEC(1000 * CALIBRATION_INTERVAL));
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}
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}
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}
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static void smartbond_start_rcx(void)
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{
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if (!lpc_clock_state.rcx_started) {
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lpc_clock_state.rcx_ready = false;
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da1469x_clock_lp_rcx_enable();
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lpc_clock_state.rcx_started = true;
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}
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if (!lpc_clock_state.rcx_ready && (CALIBRATION_INTERVAL > 0)) {
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if (!k_work_is_pending(&calibration_work.work)) {
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k_work_schedule(&calibration_work,
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K_MSEC(1000 * CALIBRATION_INTERVAL));
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}
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}
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}
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static void smartbond_start_xtal32k(void)
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{
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if (!lpc_clock_state.xtal32k_started) {
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lpc_clock_state.xtal32k_ready = false;
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da1469x_clock_lp_xtal32k_enable();
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lpc_clock_state.xtal32k_started = true;
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k_work_schedule(&xtal32k_settle_work,
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K_MSEC(DT_PROP(DT_NODELABEL(xtal32k),
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settle_time)));
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}
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}
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static inline int smartbond_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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enum smartbond_clock clk = (enum smartbond_clock)(sub_system);
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ARG_UNUSED(dev);
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switch (clk) {
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case SMARTBOND_CLK_RC32K:
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smartbond_start_rc32k();
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break;
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case SMARTBOND_CLK_RCX:
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smartbond_start_rcx();
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break;
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case SMARTBOND_CLK_XTAL32K:
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smartbond_start_xtal32k();
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break;
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case SMARTBOND_CLK_RC32M:
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CRG_TOP->CLK_RC32M_REG |= CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;
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break;
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case SMARTBOND_CLK_XTAL32M:
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da1469x_clock_sys_xtal32m_init();
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da1469x_clock_sys_xtal32m_enable();
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break;
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case SMARTBOND_CLK_PLL96M:
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if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) == 0) {
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if ((CRG_TOP->CLK_CTRL_REG &
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CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk) == 0) {
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da1469x_clock_sys_xtal32m_init();
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da1469x_clock_sys_xtal32m_enable();
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da1469x_clock_sys_xtal32m_wait_to_settle();
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}
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da1469x_clock_sys_pll_enable();
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static inline int smartbond_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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enum smartbond_clock clk = (enum smartbond_clock)(sub_system);
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ARG_UNUSED(dev);
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switch (clk) {
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case SMARTBOND_CLK_RC32K:
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if (((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) != 0) {
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CRG_TOP->CLK_RC32K_REG &= ~CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk;
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lpc_clock_state.rc32k_ready = false;
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lpc_clock_state.rc32k_started = false;
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}
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break;
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case SMARTBOND_CLK_RCX:
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if (((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) != 1) {
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CRG_TOP->CLK_RCX_REG &= ~CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk;
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lpc_clock_state.rcx_ready = false;
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lpc_clock_state.rcx_started = false;
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}
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break;
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case SMARTBOND_CLK_XTAL32K:
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if (((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) > 1) {
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CRG_TOP->CLK_XTAL32K_REG &= ~CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;
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lpc_clock_state.xtal32k_ready = false;
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lpc_clock_state.xtal32k_started = false;
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}
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break;
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case SMARTBOND_CLK_RC32M:
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/* Disable rc32m only if not used as system clock */
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if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) == 0) {
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da1469x_clock_sys_rc32m_disable();
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}
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break;
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case SMARTBOND_CLK_XTAL32M:
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da1469x_clock_sys_xtal32m_init();
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da1469x_clock_sys_xtal32m_enable();
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break;
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case SMARTBOND_CLK_PLL96M:
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da1469x_clock_sys_pll_disable();
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk)
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{
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static const enum smartbond_clock lp_clk_src[] = {
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SMARTBOND_CLK_RC32K,
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SMARTBOND_CLK_RCX,
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SMARTBOND_CLK_XTAL32K,
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SMARTBOND_CLK_XTAL32K,
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};
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static const enum smartbond_clock sys_clk_src[] = {
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SMARTBOND_CLK_XTAL32M,
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SMARTBOND_CLK_RC32M,
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SMARTBOND_CLK_LP_CLK,
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SMARTBOND_CLK_PLL96M,
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};
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if (clk == SMARTBOND_CLK_SYS_CLK) {
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clk = sys_clk_src[CRG_TOP->CLK_CTRL_REG &
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CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk];
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}
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/* System clock can be low power clock, so next check is not in else */
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if (clk == SMARTBOND_CLK_LP_CLK) {
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clk = lp_clk_src[(CRG_TOP->CLK_CTRL_REG &
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
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CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos];
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}
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return clk;
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}
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static int smartbond_clock_get_rate(enum smartbond_clock clk, uint32_t *rate)
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{
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clk = smartbond_source_clock(clk);
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switch (clk) {
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case SMARTBOND_CLK_RC32K:
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*rate = lpc_clock_state.rc32k_freq;
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break;
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case SMARTBOND_CLK_RCX:
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*rate = lpc_clock_state.rcx_freq;
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break;
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case SMARTBOND_CLK_XTAL32K:
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*rate = DT_PROP(DT_NODELABEL(xtal32k), clock_frequency);
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break;
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case SMARTBOND_CLK_RC32M:
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*rate = DT_PROP(DT_NODELABEL(rc32m), clock_frequency);
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break;
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case SMARTBOND_CLK_XTAL32M:
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*rate = DT_PROP(DT_NODELABEL(xtal32m), clock_frequency);
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break;
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case SMARTBOND_CLK_PLL96M:
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*rate = DT_PROP(DT_NODELABEL(pll), clock_frequency);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int smartbond_clock_control_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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return smartbond_clock_get_rate((enum smartbond_clock)(sub_system), rate);
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}
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static enum smartbond_clock smartbond_dt_ord_to_clock(uint32_t dt_ord)
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{
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switch (dt_ord) {
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case DT_DEP_ORD(DT_NODELABEL(rc32k)):
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return SMARTBOND_CLK_RC32K;
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case DT_DEP_ORD(DT_NODELABEL(rcx)):
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return SMARTBOND_CLK_RCX;
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case DT_DEP_ORD(DT_NODELABEL(xtal32k)):
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return SMARTBOND_CLK_XTAL32K;
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case DT_DEP_ORD(DT_NODELABEL(rc32m)):
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return SMARTBOND_CLK_RC32M;
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case DT_DEP_ORD(DT_NODELABEL(xtal32m)):
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return SMARTBOND_CLK_XTAL32M;
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case DT_DEP_ORD(DT_NODELABEL(pll)):
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return SMARTBOND_CLK_PLL96M;
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default:
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return SMARTBOND_CLK_NONE;
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}
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}
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static void smartbond_clock_control_on_by_ord(const struct device *dev,
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uint32_t clock_id)
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{
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enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id);
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smartbond_clock_control_on(dev, (clock_control_subsys_rate_t)clk);
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}
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static void smartbond_clock_control_off_by_ord(const struct device *dev,
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uint32_t clock_id)
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{
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enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id);
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smartbond_clock_control_off(dev, (clock_control_subsys_rate_t)clk);
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}
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static void
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qspi_set_read_pipe_delay(uint8_t delay)
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{
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QSPIC->QSPIC_CTRLMODE_REG =
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(QSPIC->QSPIC_CTRLMODE_REG & ~QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk) |
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(delay << QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos) |
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QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk;
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}
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static void
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qspi_set_cs_delay(uint32_t sys_clock_freq, uint32_t read_delay_ns, uint32_t erase_delay_ns)
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{
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sys_clock_freq /= 100000;
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uint32_t read_delay_cyc = ((read_delay_ns * sys_clock_freq) + 9999) / 10000;
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uint32_t erase_delay_cyc = ((erase_delay_ns * sys_clock_freq) + 9999) / 10000;
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QSPIC->QSPIC_BURSTCMDB_REG =
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(QSPIC->QSPIC_BURSTCMDB_REG & ~QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk) |
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read_delay_cyc << QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos;
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QSPIC->QSPIC_ERASECMDB_REG =
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(QSPIC->QSPIC_ERASECMDB_REG & ~QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk) |
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(erase_delay_cyc << QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos);
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}
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int z_smartbond_select_lp_clk(enum smartbond_clock lp_clk)
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{
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int rc = 0;
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uint32_t clk_sel = 0;
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uint32_t clk_sel_msk = CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk;
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switch (lp_clk) {
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case SMARTBOND_CLK_RC32K:
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clk_sel = 0;
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break;
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case SMARTBOND_CLK_RCX:
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clk_sel = 1 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos;
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break;
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case SMARTBOND_CLK_XTAL32K:
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clk_sel = 2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos;
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break;
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default:
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rc = -EINVAL;
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}
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if (rc == 0) {
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CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG & ~clk_sel_msk) | clk_sel;
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}
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return rc;
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}
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int z_smartbond_select_sys_clk(enum smartbond_clock sys_clk)
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{
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uint32_t sys_clock_freq;
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uint32_t clk_sel;
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uint32_t clk_sel_msk = CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
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int res;
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res = smartbond_clock_get_rate(sys_clk, &sys_clock_freq);
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if (res != 0) {
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return -EINVAL;
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}
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/* When PLL is selected as system clock qspi read pipe delay must be set to 7 */
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if (sys_clock_freq > 32000000) {
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qspi_set_read_pipe_delay(7);
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qspi_set_cs_delay(SystemCoreClock,
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DT_PROP(DT_NODELABEL(flash_controller),
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read_cs_idle_delay),
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DT_PROP(DT_NODELABEL(flash_controller),
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erase_cs_idle_delay));
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}
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if (sys_clk == SMARTBOND_CLK_RC32M) {
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clk_sel = 1 << CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos;
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CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG & ~clk_sel_msk) | clk_sel;
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SystemCoreClock = sys_clock_freq;
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} else if (sys_clk == SMARTBOND_CLK_PLL96M) {
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da1469x_clock_pll_wait_to_lock();
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da1469x_clock_sys_pll_switch();
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} else if (sys_clk == SMARTBOND_CLK_XTAL32M) {
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da1469x_clock_sys_xtal32m_switch_safe();
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}
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/* When switching back from PLL to 32MHz read pipe delay may be set to 2 */
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if (SystemCoreClock <= 32000000) {
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qspi_set_read_pipe_delay(2);
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qspi_set_cs_delay(SystemCoreClock,
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DT_PROP(DT_NODELABEL(flash_controller),
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read_cs_idle_delay),
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DT_PROP(DT_NODELABEL(flash_controller),
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erase_cs_idle_delay));
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}
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return 0;
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}
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/**
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* @brief Initialize clocks for the Smartbond
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*
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* This routine is called to enable and configure the clocks and PLL
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* of the soc on the board.
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*
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* @param dev clocks device struct
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*
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* @return 0
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*/
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int smartbond_clocks_init(const struct device *dev)
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{
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uint32_t clk_id;
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enum smartbond_clock lp_clk;
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enum smartbond_clock sys_clk;
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ARG_UNUSED(dev);
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#define ENABLE_OSC(clock) smartbond_clock_control_on_by_ord(dev, DT_DEP_ORD(clock))
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#define DISABLE_OSC(clock) if (DT_NODE_HAS_STATUS(clock, disabled)) { \
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smartbond_clock_control_off_by_ord(dev, DT_DEP_ORD(clock)); \
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}
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/* Enable all oscillators with status "okay" */
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DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(crg, osc), ENABLE_OSC, (;));
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/* Make sure that selected sysclock is enabled */
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BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_PROP(DT_NODELABEL(sys_clk), clock_src), okay),
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"Clock selected as system clock no enabled in DT");
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BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_PROP(DT_NODELABEL(lp_clk), clock_src), okay),
|
|
"Clock selected as LP clock no enabled in DT");
|
|
BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(pll), disabled) ||
|
|
DT_NODE_HAS_STATUS(DT_NODELABEL(xtal32m), okay),
|
|
"PLL enabled in DT but XTAL32M is disabled");
|
|
|
|
clk_id = DT_DEP_ORD(DT_PROP(DT_NODELABEL(lp_clk), clock_src));
|
|
lp_clk = smartbond_dt_ord_to_clock(clk_id);
|
|
z_smartbond_select_lp_clk(lp_clk);
|
|
|
|
clk_id = DT_DEP_ORD(DT_PROP(DT_NODELABEL(sys_clk), clock_src));
|
|
sys_clk = smartbond_dt_ord_to_clock(clk_id);
|
|
smartbond_clock_control_on(dev,
|
|
(clock_control_subsys_rate_t)smartbond_source_clock(sys_clk));
|
|
z_smartbond_select_sys_clk(sys_clk);
|
|
|
|
/* Disable unwanted oscillators */
|
|
DT_FOREACH_CHILD_SEP(DT_PATH(crg, osc), DISABLE_OSC, (;));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clock_control_driver_api smartbond_clock_control_api = {
|
|
.on = smartbond_clock_control_on,
|
|
.off = smartbond_clock_control_off,
|
|
.get_rate = smartbond_clock_control_get_rate,
|
|
};
|
|
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(osc),
|
|
&smartbond_clocks_init,
|
|
NULL,
|
|
NULL, NULL,
|
|
PRE_KERNEL_1,
|
|
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
|
&smartbond_clock_control_api);
|