593 lines
18 KiB
C
593 lines
18 KiB
C
/*
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* Copyright (c) 2010-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief IA-32 specific nanokernel interface header
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* This header contains the IA-32 specific nanokernel interface. It is included
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* by the generic nanokernel interface header (nanokernel.h)
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*/
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#ifndef _ARCH_IFACE_H
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#define _ARCH_IFACE_H
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#include <irq.h>
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#ifndef _ASMLANGUAGE
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#include <arch/x86/asm_inline.h>
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#include <arch/x86/addr_types.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* APIs need to support non-byte addressable architectures */
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#define OCTET_TO_SIZEOFUNIT(X) (X)
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#define SIZEOFUNIT_TO_OCTET(X) (X)
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/**
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* Macro used internally by NANO_CPU_INT_REGISTER and NANO_CPU_INT_REGISTER_ASM.
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* Not meant to be used explicitly by platform, driver or application code.
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*/
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#define MK_ISR_NAME(x) __isr__##x
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#ifdef CONFIG_MICROKERNEL
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#define ALL_DYN_IRQ_STUBS (CONFIG_NUM_DYNAMIC_STUBS + CONFIG_MAX_NUM_TASK_IRQS)
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#elif defined(CONFIG_NANOKERNEL)
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#define ALL_DYN_IRQ_STUBS (CONFIG_NUM_DYNAMIC_STUBS)
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#endif
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#define ALL_DYN_EXC_STUBS (CONFIG_NUM_DYNAMIC_EXC_STUBS + \
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CONFIG_NUM_DYNAMIC_EXC_NOERR_STUBS)
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#define ALL_DYN_STUBS (ALL_DYN_EXC_STUBS + ALL_DYN_IRQ_STUBS)
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/*
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* Synchronize these DYN_STUB_* macros with the generated assembly for
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* _DynIntStubsBegin in intstub.S / _DynExcStubsBegin in excstub.S
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* Assumes all stub types are same size/format
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*/
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/* Size of each dynamic interrupt/exception stub in bytes */
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#ifdef CONFIG_X86_IAMCU
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#define DYN_STUB_SIZE 8
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#else
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#define DYN_STUB_SIZE 9
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#endif
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/*
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* Offset from the beginning of a stub to the byte containing the argument
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* to the push instruction, which is the stub index
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*/
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#define DYN_STUB_IDX_OFFSET 6
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/* Every DYN_STUB_PER_BLOCK stubs, there is a long jump instead of
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* a short jump. Define the extra amount of bytes for this.
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*/
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#define DYN_STUB_LONG_JMP_EXTRA_SIZE 3
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/*
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* How many consecutive stubs we have until we encounter a periodic
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* jump to _DynStubCommon
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*/
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#define DYN_STUB_PER_BLOCK 8
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#ifndef _ASMLANGUAGE
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/* interrupt/exception/error related definitions */
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/**
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* Floating point register set alignment.
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*
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* If support for SSEx extensions is enabled a 16 byte boundary is required,
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* since the 'fxsave' and 'fxrstor' instructions require this. In all other
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* cases a 4 byte boundary is sufficient.
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*/
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#ifdef CONFIG_SSE
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#define FP_REG_SET_ALIGN 16
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#else
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#define FP_REG_SET_ALIGN 4
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#endif
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/*
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* The TCS must be aligned to the same boundary as that used by the floating
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* point register set. This applies even for threads that don't initially
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* use floating point, since it is possible to enable floating point support
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* later on.
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*/
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#define STACK_ALIGN FP_REG_SET_ALIGN
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typedef struct s_isrList {
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/** Address of ISR/stub */
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void *fnc;
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/** IRQ associated with the ISR/stub */
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unsigned int irq;
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/** Priority associated with the IRQ */
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unsigned int priority;
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/** Vector number associated with ISR/stub */
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unsigned int vec;
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/** Privilege level associated with ISR/stub */
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unsigned int dpl;
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} ISR_LIST;
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/**
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* @brief Connect a routine to an interrupt vector
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*
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* This macro "connects" the specified routine, @a r, to the specified interrupt
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* vector, @a v using the descriptor privilege level @a d. On the IA-32
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* architecture, an interrupt vector is a value from 0 to 255. This macro
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* populates the special intList section with the address of the routine, the
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* vector number and the descriptor privilege level. The genIdt tool then picks
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* up this information and generates an actual IDT entry with this information
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* properly encoded. This macro replaces the _IntVecSet () routine in static
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* interrupt systems.
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*
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* The @a d argument specifies the privilege level for the interrupt-gate
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* descriptor; (hardware) interrupts and exceptions should specify a level of 0,
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* whereas handlers for user-mode software generated interrupts should specify 3.
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* @param r Routine to be connected
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* @param n IRQ number
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* @param p IRQ priority
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* @param v Interrupt Vector
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* @param d Descriptor Privilege Level
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*
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* @return N/A
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*
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*/
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#define NANO_CPU_INT_REGISTER(r, n, p, v, d) \
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ISR_LIST __attribute__((section(".intList"))) MK_ISR_NAME(r) = \
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{&r, n, p, v, d}
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/**
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* Inline assembly code for the interrupt stub
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*
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* This is the actual assembly code which gets run when the interrupt
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* is triggered. Due to different calling convention semantics we have
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* different versions for IAMCU and SYSV.
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*
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* For IAMCU case, we call _execute_handler() with the isr and its argument
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* as parameters.
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*
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* For SysV case, we first call _IntEnt to properly enter Zephyr's interrupt
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* handling context, and then directly call the isr. A jump is done to
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* _IntExitWithEoi which does EOI to the interrupt controller, restores
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* context, and finally does 'iret'.
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*
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* This is only intended to be used by the IRQ_CONNECT() macro.
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*/
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#if CONFIG_X86_IAMCU
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#define _IRQ_STUB_ASM \
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"pushl %%eax\n\t" \
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"pushl %%edx\n\t" \
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"pushl %%ecx\n\t" \
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"movl %[isr], %%eax\n\t" \
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"movl %[isr_param], %%edx\n\t" \
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"call _execute_handler\n\t" \
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"popl %%ecx\n\t" \
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"popl %%edx\n\t" \
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"popl %%eax\n\t" \
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"iret\n\t"
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#else
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#define _IRQ_STUB_ASM \
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"call _IntEnt\n\t" \
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"pushl %[isr_param]\n\t" \
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"call %P[isr]\n\t" \
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"jmp _IntExitWithEoi\n\t"
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#endif /* CONFIG_X86_IAMCU */
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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#define _IRQ_STUB_LABEL \
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" .global %[isr]%P[irq]_stub\n\t" \
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"%[isr]%P[irq]_stub:\n\t"
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#else
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#define _IRQ_STUB_LABEL
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#endif
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/**
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* Code snippets for populating the vector ID and priority into the intList
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*
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* The 'magic' of static interrupts is accomplished by building up an array
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* 'intList' at compile time, and the gen_idt tool uses this to create the
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* actual IDT data structure.
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*
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* For controllers like APIC, the vectors in the IDT are not normally assigned
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* at build time; instead the sentinel value -1 is saved, and gen_idt figures
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* out the right vector to use based on our priority scheme. Groups of 16
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* vectors starting at 32 correspond to each priority level.
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*
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* On MVIC, the mapping is fixed; the vector to use is just the irq line
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* number plus 0x20. The priority argument supplied by the user is discarded.
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*
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* These macros are only intended to be used by IRQ_CONNECT() macro.
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*/
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#if CONFIG_MVIC
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#define _PRIORITY_ARG(irq_p, priority_p) (-1)
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#define _VECTOR_ARG(irq_p) (irq_p + 0x20)
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#else
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#define _PRIORITY_ARG(irq_p, priority_p) (priority_p)
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#define _VECTOR_ARG(irq_p) (-1)
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#endif /* CONFIG_MVIC */
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time; if this
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* can't be done use irq_connect_dynamic() instead.
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*
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* Internally this function does a few things:
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*
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* 1. There is a block of inline assembly which is completely skipped over
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* at runtime with an initial 'jmp' instruction.
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*
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* 2. There is a declaration of the interrupt parameters in the .intList
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* section, used by gen_idt to create the IDT. This does the same thing
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* as the NANO_CPU_INT_REGISTER() macro, but is done in assembly as we
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* need to populate the .fnc member with the address of the assembly
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* IRQ stub that we generate immediately afterwards.
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*
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* 3. The IRQ stub itself is declared. It doesn't get run in the context
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* of the calling function due to the initial 'jmp' instruction at the
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* beginning of the assembly block, but a pointer to it gets saved in the IDT.
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*
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* 4. _SysIntVecProgram() is called at runtime to set the mapping between
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* the vector and the IRQ line.
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ triggering options
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*
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* @return The vector assigned to this interrupt
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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__asm__ __volatile__( \
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"jmp 2f\n\t" \
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".pushsection .intList\n\t" \
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".long 1f\n\t" /* ISR_LIST.fnc */ \
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".long %P[irq]\n\t" /* ISR_LIST.irq */ \
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".long %P[priority]\n\t" /* ISR_LIST.priority */ \
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".long %P[vector]\n\t" /* ISR_LIST.vec */ \
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".long 0\n\t" /* ISR_LIST.dpl */ \
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".popsection\n\t" \
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"1:\n\t" \
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_IRQ_STUB_LABEL \
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_IRQ_STUB_ASM \
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"2:\n\t" \
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: \
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: [isr] "i" (isr_p), \
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[isr_param] "i" (isr_param_p), \
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[priority] "i" _PRIORITY_ARG(irq_p, priority_p), \
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[vector] "i" _VECTOR_ARG(irq_p), \
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[irq] "i" (irq_p)); \
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_SysIntVecProgram(_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), (flags_p)); \
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_IRQ_TO_INTERRUPT_VECTOR(irq_p); \
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})
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#ifdef CONFIG_MVIC
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/* Fixed vector-to-irq association mapping.
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* No need for the table at all.
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*/
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#define _IRQ_TO_INTERRUPT_VECTOR(irq) (irq + 0x20)
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#else
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/**
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* @brief Convert a statically connected IRQ to its interrupt vector number
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*
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* @param irq IRQ number
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*/
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extern unsigned char _irq_to_interrupt_vector[];
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#define _IRQ_TO_INTERRUPT_VECTOR(irq) \
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((unsigned int) _irq_to_interrupt_vector[irq])
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#endif
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/**
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* @brief Nanokernel Exception Stack Frame
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*
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* A pointer to an "exception stack frame" (ESF) is passed as an argument
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* to exception handlers registered via nanoCpuExcConnect(). As the system
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* always operates at ring 0, only the EIP, CS and EFLAGS registers are pushed
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* onto the stack when an exception occurs.
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*
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* The exception stack frame includes the volatile registers (EAX, ECX, and
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* EDX) as well as the 5 non-volatile registers (EDI, ESI, EBX, EBP and ESP).
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* Those registers are pushed onto the stack by _ExcEnt().
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*/
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typedef struct nanoEsf {
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unsigned int esp;
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unsigned int ebp;
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unsigned int ebx;
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unsigned int esi;
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unsigned int edi;
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unsigned int edx;
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unsigned int eax;
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unsigned int ecx;
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unsigned int errorCode;
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unsigned int eip;
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unsigned int cs;
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unsigned int eflags;
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} NANO_ESF;
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/**
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* @brief Nanokernel "interrupt stack frame" (ISF)
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*
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* An "interrupt stack frame" (ISF) as constructed by the processor
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* and the interrupt wrapper function _IntEnt(). As the system always operates
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* at ring 0, only the EIP, CS and EFLAGS registers are pushed onto the stack
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* when an interrupt occurs.
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*
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* The interrupt stack frame includes the volatile registers EAX, ECX, and EDX
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* pushed on the stack by _IntEnt().
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*
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* Only target-based debug tools such as GDB require the 5 non-volatile
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* registers (EDI, ESI, EBX, EBP and ESP) to be preserved during an interrupt.
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*/
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typedef struct nanoIsf {
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#ifdef CONFIG_DEBUG_INFO
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unsigned int esp;
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unsigned int ebp;
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unsigned int ebx;
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unsigned int esi;
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unsigned int edi;
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#endif /* CONFIG_DEBUG_INFO */
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unsigned int edx;
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unsigned int ecx;
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unsigned int eax;
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unsigned int eip;
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unsigned int cs;
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unsigned int eflags;
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} NANO_ISF;
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#endif /* !_ASMLANGUAGE */
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/*
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* Reason codes passed to both _NanoFatalErrorHandler()
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* and _SysFatalErrorHandler().
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*/
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/** Unhandled exception/interrupt */
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#define _NANO_ERR_SPURIOUS_INT (0)
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/** Page fault */
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#define _NANO_ERR_PAGE_FAULT (1)
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/** General protection fault */
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#define _NANO_ERR_GEN_PROT_FAULT (2)
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/** Invalid task exit */
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#define _NANO_ERR_INVALID_TASK_EXIT (3)
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/** Stack corruption detected */
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#define _NANO_ERR_STACK_CHK_FAIL (4)
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/** Kernel Allocation Failure */
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#define _NANO_ERR_ALLOCATION_FAIL (5)
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/** Unhandled exception */
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#define _NANO_ERR_CPU_EXCEPTION (6)
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#ifndef _ASMLANGUAGE
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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void _int_latency_start(void);
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void _int_latency_stop(void);
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#else
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#define _int_latency_start() do { } while (0)
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#define _int_latency_stop() do { } while (0)
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#endif
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/**
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* @brief Disable all interrupts on the CPU (inline)
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*
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* This routine disables interrupts. It can be called from either interrupt,
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* task or fiber level. This routine returns an architecture-dependent
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* lock-out key representing the "interrupt disable state" prior to the call;
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* this key can be passed to irq_unlock() to re-enable interrupts.
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*
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* The lock-out key should only be used as the argument to the irq_unlock()
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* API. It should never be used to manually re-enable interrupts or to inspect
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* or manipulate the contents of the source register.
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*
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* This function can be called recursively: it will return a key to return the
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* state of interrupt locking to the previous level.
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*
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* WARNINGS
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* Invoking a kernel routine with interrupts locked may result in
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* interrupts being re-enabled for an unspecified period of time. If the
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* called routine blocks, interrupts will be re-enabled while another
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* thread executes, or while the system is idle.
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*
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* The "interrupt disable state" is an attribute of a thread. Thus, if a
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* fiber or task disables interrupts and subsequently invokes a kernel
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* routine that causes the calling thread to block, the interrupt
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* disable state will be restored when the thread is later rescheduled
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* for execution.
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*
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* @return An architecture-dependent lock-out key representing the
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* "interrupt disable state" prior to the call.
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*
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*/
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static inline __attribute__((always_inline)) unsigned int _arch_irq_lock(void)
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{
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unsigned int key = _do_irq_lock();
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_int_latency_start();
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return key;
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}
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/**
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*
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* @brief Enable all interrupts on the CPU (inline)
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*
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* This routine re-enables interrupts on the CPU. The @a key parameter
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* is an architecture-dependent lock-out key that is returned by a previous
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* invocation of irq_lock().
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*
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* This routine can be called from either interrupt, task or fiber level.
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*
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* @return N/A
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*
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*/
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static inline __attribute__((always_inline)) void _arch_irq_unlock(unsigned int key)
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{
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if (!(key & 0x200)) {
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return;
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}
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_int_latency_stop();
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_do_irq_unlock();
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}
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/** interrupt/exception/error related definitions */
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typedef void (*NANO_EOI_GET_FUNC) (void *);
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/**
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* The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter
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* to NANO_CPU_INT_REGSITER when connecting to an interrupt that does not
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* correspond to any IRQ line (such as spurious vector or SW IRQ)
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*/
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#define NANO_SOFT_IRQ ((unsigned int) (-1))
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#ifdef CONFIG_FP_SHARING
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/* Definitions for the 'options' parameter to the fiber_fiber_start() API */
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/** thread uses floating point unit */
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#define USE_FP 0x10
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#ifdef CONFIG_SSE
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/** thread uses SSEx instructions */
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#define USE_SSE 0x20
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#endif /* CONFIG_SSE */
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#endif /* CONFIG_FP_SHARING */
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extern int _arch_irq_connect_dynamic(unsigned int irq,
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unsigned int priority,
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void (*routine)(void *parameter),
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void *parameter,
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uint32_t flags);
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/**
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* @brief Enable a specific IRQ
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* @param irq IRQ
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*/
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extern void _arch_irq_enable(unsigned int irq);
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/**
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* @brief Disable a specific IRQ
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* @param irq IRQ
|
|
*/
|
|
extern void _arch_irq_disable(unsigned int irq);
|
|
|
|
#ifdef CONFIG_FP_SHARING
|
|
/**
|
|
* @brief Enable floating point hardware resources sharing
|
|
* Dynamically enable/disable the capability of a thread to share floating
|
|
* point hardware resources. The same "floating point" options accepted by
|
|
* fiber_fiber_start() are accepted by these APIs (i.e. USE_FP and USE_SSE).
|
|
*/
|
|
extern void fiber_float_enable(nano_thread_id_t thread_id,
|
|
unsigned int options);
|
|
extern void task_float_enable(nano_thread_id_t thread_id,
|
|
unsigned int options);
|
|
extern void fiber_float_disable(nano_thread_id_t thread_id);
|
|
extern void task_float_disable(nano_thread_id_t thread_id);
|
|
#endif /* CONFIG_FP_SHARING */
|
|
|
|
#include <stddef.h> /* for size_t */
|
|
|
|
extern void nano_cpu_idle(void);
|
|
|
|
/** Nanokernel provided routine to report any detected fatal error. */
|
|
extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
|
|
const NANO_ESF * pEsf);
|
|
/** User provided routine to handle any detected fatal error post reporting. */
|
|
extern FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
|
|
const NANO_ESF * pEsf);
|
|
/** Dummy ESF for fatal errors that would otherwise not have an ESF */
|
|
extern const NANO_ESF _default_esf;
|
|
|
|
/**
|
|
* @brief Configure an interrupt vector of the specified priority
|
|
*
|
|
* This routine is invoked by the kernel to configure an interrupt vector of
|
|
* the specified priority. To this end, it allocates an interrupt vector,
|
|
* programs hardware to route interrupt requests on the specified IRQ to that
|
|
* vector, and returns the vector number
|
|
*/
|
|
extern int _SysIntVecAlloc(unsigned int irq,
|
|
unsigned int priority,
|
|
uint32_t flags);
|
|
|
|
/**
|
|
*
|
|
* @brief Program interrupt controller
|
|
*
|
|
* This routine programs the interrupt controller with the given vector
|
|
* based on the given IRQ parameter.
|
|
*
|
|
* Drivers call this routine instead of IRQ_CONNECT() when interrupts are
|
|
* configured statically.
|
|
*
|
|
*/
|
|
extern void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags);
|
|
|
|
/* functions provided by the kernel for usage by _SysIntVecAlloc() */
|
|
|
|
extern int _IntVecAlloc(unsigned int priority);
|
|
|
|
extern void _IntVecMarkAllocated(unsigned int vector);
|
|
|
|
extern void _IntVecMarkFree(unsigned int vector);
|
|
|
|
#if CONFIG_DEBUG_IRQS
|
|
/**
|
|
*
|
|
* @brief Dump out the IDT for debugging purposes
|
|
*
|
|
* The IDT has a strange structure which confounds direct examination in
|
|
* a debugger. This function will print out its contents in human-readable
|
|
* form. If unused, gc-sections will strip this function from the binary.
|
|
*/
|
|
void irq_debug_dump_idt(void);
|
|
#endif /* CONFIG_DEBUG_IRQS */
|
|
|
|
#endif /* !_ASMLANGUAGE */
|
|
|
|
/* Segment selector definitions are shared */
|
|
#include "segselect.h"
|
|
|
|
/* reboot through Reset Control Register (I/O port 0xcf9) */
|
|
|
|
#define SYS_X86_RST_CNT_REG 0xcf9
|
|
#define SYS_X86_RST_CNT_SYS_RST 0x02
|
|
#define SYS_X86_RST_CNT_CPU_RST 0x4
|
|
#define SYS_X86_RST_CNT_FULL_RST 0x08
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _ARCH_IFACE_H */
|