323 lines
6.8 KiB
C
323 lines
6.8 KiB
C
/* asm_inline_gcc.h - ARC inline assembler and macros for public functions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ASM_INLINE_GCC_H__
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#define __ASM_INLINE_GCC_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include <sys_io.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <stdint.h>
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#include <stddef.h>
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/* Implementation of sys_io.h's documented functions */
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static inline __attribute__((always_inline))
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void sys_out8(uint8_t data, io_port_t port)
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{
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_arc_v2_aux_reg_write(port, data);
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}
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static inline __attribute__((always_inline))
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uint8_t sys_in8(io_port_t port)
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{
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return (uint8_t)(_arc_v2_aux_reg_read(port) & 0x000000ff);
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}
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static inline __attribute__((always_inline))
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void sys_out16(uint16_t data, io_port_t port)
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{
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_arc_v2_aux_reg_write(port, data);
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}
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static inline __attribute__((always_inline))
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uint16_t sys_in16(io_port_t port)
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{
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return (uint16_t)(_arc_v2_aux_reg_read(port) & 0x0000ffff);
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}
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static inline __attribute__((always_inline))
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void sys_out32(uint32_t data, io_port_t port)
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{
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_arc_v2_aux_reg_write(port, data);
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}
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static inline __attribute__((always_inline))
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uint32_t sys_in32(io_port_t port)
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{
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return _arc_v2_aux_reg_read(port);
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}
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static inline __attribute__((always_inline))
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void sys_io_set_bit(io_port_t port, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bset %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static inline __attribute__((always_inline))
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void sys_io_clear_bit(io_port_t port, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bclr %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static inline __attribute__((always_inline))
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int sys_io_test_bit(io_port_t port, unsigned int bit)
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{
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uint32_t status = _ARC_V2_STATUS32;
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uint32_t reg = 0;
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uint32_t ret;
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__asm__ volatile("lr %2, [%1]\n"
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"btst %2, %3\n"
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"lr %0, [%4];\n\t"
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: "=r" (ret)
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: "ir" (port),
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"r" (reg), "Mr" (bit), "i" (status)
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: "memory", "cc");
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return !(ret & _ARC_V2_STATUS32_Z);
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}
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static inline __attribute__((always_inline))
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int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_set_bit(port, bit);
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return ret;
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}
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static inline __attribute__((always_inline))
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int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_clear_bit(port, bit);
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return ret;
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}
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static inline __attribute__((always_inline))
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void sys_write8(uint8_t data, mm_reg_t addr)
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{
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__asm__ volatile("stb%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile uint8_t *) addr)
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: "memory");
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}
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static inline __attribute__((always_inline))
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uint8_t sys_read8(mm_reg_t addr)
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{
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uint8_t ret;
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__asm__ volatile("ldb%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile uint8_t *) addr)
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: "memory");
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return ret;
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}
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static inline __attribute__((always_inline))
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void sys_write16(uint16_t data, mm_reg_t addr)
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{
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__asm__ volatile("sth%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile uint16_t *) addr)
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: "memory");
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}
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static inline __attribute__((always_inline))
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uint16_t sys_read16(mm_reg_t addr)
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{
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uint16_t ret;
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__asm__ volatile("ldh%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile uint16_t *) addr)
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: "memory");
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return ret;
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}
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static inline __attribute__((always_inline))
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void sys_write32(uint32_t data, mm_reg_t addr)
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{
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__asm__ volatile("st%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile uint32_t *) addr)
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: "memory");
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}
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static inline __attribute__((always_inline))
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uint32_t sys_read32(mm_reg_t addr)
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{
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uint32_t ret;
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__asm__ volatile("ld%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile uint32_t *) addr)
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: "memory");
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return ret;
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}
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static inline __attribute__((always_inline))
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void sys_set_bit(mem_addr_t addr, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("ld %1, %0\n"
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"bset %1, %1, %2\n"
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"st %1, %0;\n\t"
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: "+m" (*(volatile uint32_t *) addr)
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: "r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static inline __attribute__((always_inline))
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void sys_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("ld %1, %0\n"
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"bclr %1, %1, %2\n"
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"st %1, %0;\n\t"
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: "+m" (*(volatile uint32_t *) addr)
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: "r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static inline __attribute__((always_inline))
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int sys_test_bit(mem_addr_t addr, unsigned int bit)
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{
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uint32_t status = _ARC_V2_STATUS32;
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uint32_t reg = 0;
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uint32_t ret;
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__asm__ volatile("ld %2, %1\n"
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"btst %2, %3\n"
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"lr %0, [%4];\n\t"
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: "=r" (ret)
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: "m" (*(volatile uint32_t *) addr),
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"r" (reg), "Mr" (bit), "i" (status)
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: "memory", "cc");
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return !(ret & _ARC_V2_STATUS32_Z);
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}
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static inline __attribute__((always_inline))
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int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_test_bit(addr, bit);
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sys_set_bit(addr, bit);
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return ret;
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}
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static inline __attribute__((always_inline))
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int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_test_bit(addr, bit);
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sys_clear_bit(addr, bit);
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return ret;
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}
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static inline __attribute__((always_inline))
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void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
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{
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/* Doing memory offsets in terms of 32-bit values to prevent
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* alignment issues
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*/
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sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static inline __attribute__((always_inline))
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void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static inline __attribute__((always_inline))
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int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
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{
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return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static inline __attribute__((always_inline))
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int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_bitfield_test_bit(addr, bit);
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sys_bitfield_set_bit(addr, bit);
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return ret;
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}
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static inline __attribute__((always_inline))
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int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_bitfield_test_bit(addr, bit);
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sys_bitfield_clear_bit(addr, bit);
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return ret;
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASM_INLINE_GCC_H__ */
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