339 lines
8.7 KiB
C
339 lines
8.7 KiB
C
/*
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* Copyright (c) 2011-2014 Wind River Systems, Inc.
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <mmustructs.h>
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#include <linker/linker-defs.h>
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#include <kernel_internal.h>
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#include <init.h>
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/* Common regions for all x86 processors.
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* Peripheral I/O ranges configured at the SOC level
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*/
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/* Mark text and rodata as read-only.
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* Userspace may read all text and rodata.
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*/
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MMU_BOOT_REGION((u32_t)&_image_rom_start, (u32_t)&_image_rom_size,
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MMU_ENTRY_READ | MMU_ENTRY_USER);
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#ifdef CONFIG_APPLICATION_MEMORY
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/* User threads by default can read/write app-level memory. */
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MMU_BOOT_REGION((u32_t)&__app_ram_start, (u32_t)&__app_ram_size,
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MMU_ENTRY_WRITE | MMU_ENTRY_USER | MMU_ENTRY_EXECUTE_DISABLE);
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#endif
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#ifdef CONFIG_APP_SHARED_MEM
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MMU_BOOT_REGION((u32_t)&_app_smem_start, (u32_t)&_app_smem_size,
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MMU_ENTRY_WRITE | MMU_ENTRY_USER | MMU_ENTRY_EXECUTE_DISABLE);
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#endif
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/* __kernel_ram_size includes all unused memory, which is used for heaps.
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* User threads cannot access this unless granted at runtime. This is done
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* automatically for stacks.
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*/
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MMU_BOOT_REGION((u32_t)&__kernel_ram_start, (u32_t)&__kernel_ram_size,
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MMU_ENTRY_WRITE |
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MMU_ENTRY_RUNTIME_USER |
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MMU_ENTRY_EXECUTE_DISABLE);
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void _x86_mmu_get_flags(void *addr,
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x86_page_entry_data_t *pde_flags,
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x86_page_entry_data_t *pte_flags)
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{
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*pde_flags = (x86_page_entry_data_t)(X86_MMU_GET_PDE(addr)->value &
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~(x86_page_entry_data_t)MMU_PDE_PAGE_TABLE_MASK);
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if (*pde_flags & MMU_ENTRY_PRESENT) {
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*pte_flags = (x86_page_entry_data_t)
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(X86_MMU_GET_PTE(addr)->value &
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~(x86_page_entry_data_t)MMU_PTE_PAGE_MASK);
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} else {
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*pte_flags = 0;
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}
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}
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int _arch_buffer_validate(void *addr, size_t size, int write)
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{
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u32_t start_pde_num;
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u32_t end_pde_num;
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u32_t starting_pte_num;
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u32_t ending_pte_num;
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u32_t pde;
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u32_t pte;
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#ifdef CONFIG_X86_PAE_MODE
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union x86_mmu_pae_pte pte_value;
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u32_t start_pdpte_num = MMU_PDPTE_NUM(addr);
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u32_t end_pdpte_num = MMU_PDPTE_NUM((char *)addr + size - 1);
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u32_t pdpte;
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#else
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union x86_mmu_pte pte_value;
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#endif
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struct x86_mmu_page_table *pte_address;
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start_pde_num = MMU_PDE_NUM(addr);
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end_pde_num = MMU_PDE_NUM((char *)addr + size - 1);
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starting_pte_num = MMU_PAGE_NUM((char *)addr);
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#ifdef CONFIG_X86_PAE_MODE
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for (pdpte = start_pdpte_num; pdpte <= end_pdpte_num; pdpte++) {
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if (pdpte != start_pdpte_num) {
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start_pde_num = 0;
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}
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if (pdpte != end_pdpte_num) {
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end_pde_num = 0;
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} else {
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end_pde_num = MMU_PDE_NUM((char *)addr + size - 1);
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}
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struct x86_mmu_page_directory *pd_address =
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X86_MMU_GET_PD_ADDR_INDEX(pdpte);
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#endif
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/* Iterate for all the pde's the buffer might take up.
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* (depends on the size of the buffer and start address
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* of the buff)
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*/
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for (pde = start_pde_num; pde <= end_pde_num; pde++) {
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#ifdef CONFIG_X86_PAE_MODE
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union x86_mmu_pae_pde pde_value =
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pd_address->entry[pde];
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#else
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union x86_mmu_pde_pt pde_value =
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X86_MMU_PD->entry[pde].pt;
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#endif
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if (!pde_value.p ||
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!pde_value.us ||
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(write && !pde_value.rw)) {
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return -EPERM;
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}
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pte_address = (struct x86_mmu_page_table *)
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(pde_value.page_table << MMU_PAGE_SHIFT);
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/* loop over all the possible page tables for the
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* required size. If the pde is not the last one
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* then the last pte would be 1023. So each pde
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* will be using all the page table entires except
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* for the last pde. For the last pde, pte is
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* calculated using the last memory address
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* of the buffer.
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*/
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if (pde != end_pde_num) {
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ending_pte_num = 1023;
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} else {
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ending_pte_num =
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MMU_PAGE_NUM((char *)addr + size - 1);
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}
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/* For all the pde's appart from the starting pde,
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* will have the start pte number as zero.
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*/
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if (pde != start_pde_num) {
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starting_pte_num = 0;
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}
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pte_value.value = 0xFFFFFFFF;
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/* Bitwise AND all the pte values.
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* An optimization done to make sure a compare is
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* done only once.
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*/
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for (pte = starting_pte_num;
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pte <= ending_pte_num;
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pte++) {
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pte_value.value &=
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pte_address->entry[pte].value;
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}
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if (!pte_value.p ||
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!pte_value.us ||
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(write && !pte_value.rw)) {
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return -EPERM;
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}
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}
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#ifdef CONFIG_X86_PAE_MODE
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}
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#endif
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return 0;
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}
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static inline void tlb_flush_page(void *addr)
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{
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/* Invalidate TLB entries corresponding to the page containing the
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* specified address
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*/
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char *page = (char *)addr;
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__asm__ ("invlpg %0" :: "m" (*page));
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}
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void _x86_mmu_set_flags(void *ptr,
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size_t size,
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x86_page_entry_data_t flags,
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x86_page_entry_data_t mask)
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{
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#ifdef CONFIG_X86_PAE_MODE
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union x86_mmu_pae_pte *pte;
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#else
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union x86_mmu_pte *pte;
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#endif
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u32_t addr = (u32_t)ptr;
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__ASSERT(!(addr & MMU_PAGE_MASK), "unaligned address provided");
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__ASSERT(!(size & MMU_PAGE_MASK), "unaligned size provided");
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while (size) {
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#ifdef CONFIG_X86_PAE_MODE
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/* TODO we're not generating 2MB entries at the moment */
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__ASSERT(X86_MMU_GET_PDE(addr)->ps != 1, "2MB PDE found");
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#else
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/* TODO we're not generating 4MB entries at the moment */
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__ASSERT(X86_MMU_GET_4MB_PDE(addr)->ps != 1, "4MB PDE found");
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#endif
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pte = X86_MMU_GET_PTE(addr);
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pte->value = (pte->value & ~mask) | flags;
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tlb_flush_page((void *)addr);
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size -= MMU_PAGE_SIZE;
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addr += MMU_PAGE_SIZE;
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}
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}
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#ifdef CONFIG_X86_USERSPACE
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/* Helper macros needed to be passed to x86_update_mem_domain_pages */
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#define X86_MEM_DOMAIN_SET_PAGES (0U)
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#define X86_MEM_DOMAIN_RESET_PAGES (1U)
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/* Pass 1 to page_conf if reset of mem domain pages is needed else pass a 0*/
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static inline void _x86_mem_domain_pages_update(struct k_mem_domain *mem_domain,
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u32_t page_conf)
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{
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u32_t partition_index;
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u32_t total_partitions;
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struct k_mem_partition partition;
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u32_t partitions_count;
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/* If mem_domain doesn't point to a valid location return.*/
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if (mem_domain == NULL) {
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goto out;
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}
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/* Get the total number of partitions*/
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total_partitions = mem_domain->num_partitions;
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/* Iterate over all the partitions for the given mem_domain
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* For x86: interate over all the partitions and set the
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* required flags in the correct MMU page tables.
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*/
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partitions_count = 0;
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for (partition_index = 0;
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partitions_count < total_partitions;
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partition_index++) {
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/* Get the partition info */
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partition = mem_domain->partitions[partition_index];
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if (partition.size == 0) {
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continue;
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}
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partitions_count++;
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if (page_conf == X86_MEM_DOMAIN_SET_PAGES) {
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/* Set the partition attributes */
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_x86_mmu_set_flags((void *)partition.start,
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partition.size,
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partition.attr,
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K_MEM_PARTITION_PERM_MASK);
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} else {
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/* Reset the pages to supervisor RW only */
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_x86_mmu_set_flags((void *)partition.start,
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partition.size,
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K_MEM_PARTITION_P_RW_U_NA,
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K_MEM_PARTITION_PERM_MASK);
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}
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}
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out:
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return;
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}
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/* Load the partitions of the thread. */
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void _arch_mem_domain_configure(struct k_thread *thread)
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{
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_x86_mem_domain_pages_update(thread->mem_domain_info.mem_domain,
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X86_MEM_DOMAIN_SET_PAGES);
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}
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/* Destroy or reset the mmu page tables when necessary.
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* Needed when either swap takes place or k_mem_domain_destroy is called.
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*/
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void _arch_mem_domain_destroy(struct k_mem_domain *domain)
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{
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_x86_mem_domain_pages_update(domain, X86_MEM_DOMAIN_RESET_PAGES);
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}
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/* Reset/destroy one partition spcified in the argument of the API. */
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void _arch_mem_domain_partition_remove(struct k_mem_domain *domain,
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u32_t partition_id)
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{
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u32_t total_partitions;
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struct k_mem_partition partition;
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if (domain == NULL) {
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goto out;
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}
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total_partitions = domain->num_partitions;
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__ASSERT(partition_id <= total_partitions,
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"invalid partitions");
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partition = domain->partitions[partition_id];
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_x86_mmu_set_flags((void *)partition.start,
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partition.size,
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K_MEM_PARTITION_P_RW_U_NA,
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K_MEM_PARTITION_PERM_MASK);
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out:
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return;
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}
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int _arch_mem_domain_max_partitions_get(void)
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{
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return CONFIG_MAX_DOMAIN_PARTITIONS;
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}
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#ifdef CONFIG_NEWLIB_LIBC
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static int newlib_mmu_prepare(struct device *unused)
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{
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ARG_UNUSED(unused);
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void *heap_base;
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size_t heap_size;
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z_newlib_get_heap_bounds(&heap_base, &heap_size);
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/* Set up the newlib heap area as a globally user-writable region.
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* We can't do this at build time with MMU_BOOT_REGION() as the _end
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* pointer shifts significantly between build phases due to the
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* introduction of page tables.
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*/
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_x86_mmu_set_flags(heap_base, heap_size,
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MMU_ENTRY_PRESENT | MMU_ENTRY_WRITE |
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MMU_ENTRY_USER,
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MMU_PTE_P_MASK | MMU_PTE_RW_MASK | MMU_PTE_US_MASK);
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return 0;
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}
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SYS_INIT(newlib_mmu_prepare, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_NEWLIB_LIBC */
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#endif /* CONFIG_X86_USERSPACE*/
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