514 lines
12 KiB
C
514 lines
12 KiB
C
/* spi_dw.c - Designware SPI driver implementation */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <sys_io.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <spi.h>
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#include <spi_dw.h>
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#endif
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#define SYS_LOG_DOMAIN "SPI DW"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
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#include <logging/sys_log.h>
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#if (CONFIG_SYS_LOG_SPI_LEVEL == 4)
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#define DBG_COUNTER_INIT() \
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u32_t __cnt = 0
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#define DBG_COUNTER_INC() \
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(__cnt++)
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#define DBG_COUNTER_RESULT() \
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(__cnt)
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#else
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#define DBG_COUNTER_INIT() {; }
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#define DBG_COUNTER_INC() {; }
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#define DBG_COUNTER_RESULT() 0
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#endif
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static void completed(struct device *dev, int error)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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if (error) {
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goto out;
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}
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/*
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* There are several situations here.
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* 1. spi_write w rx_buf - need last_tx && rx_buf_len zero to be done.
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* 2. spi_write w/o rx_buf - only need to determine when write is done.
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* 3. spi_read - need rx_buf_len zero.
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*/
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if (spi->tx_buf && spi->rx_buf) {
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if (!spi->last_tx || spi->rx_buf_len) {
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return;
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}
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} else if (spi->tx_buf) {
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if (!spi->last_tx) {
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return;
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}
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} else { /* or, spi->rx_buf!=0 */
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if (spi->rx_buf_len) {
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return;
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}
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}
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out:
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/* need to give time for FIFOs to drain before issuing more commands */
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while (test_bit_sr_busy(info->regs)) {
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}
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spi->error = error;
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/* Disabling interrupts */
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write_imr(DW_SPI_IMR_MASK, info->regs);
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/* Disabling the controller */
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clear_bit_ssienr(info->regs);
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_spi_control_cs(dev, 0);
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SYS_LOG_DBG("SPI transaction completed %s error",
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error ? "with" : "without");
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k_sem_give(&spi->device_sync_sem);
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}
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static void push_data(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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u32_t data = 0;
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u32_t f_tx;
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DBG_COUNTER_INIT();
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if (spi->rx_buf) {
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f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
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read_rxflr(info->regs);
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if ((int)f_tx < 0) {
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f_tx = 0; /* if rx-fifo is full, hold off tx */
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}
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} else {
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f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs);
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}
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if (f_tx && (spi->tx_buf_len == 0)) {
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/* room in fifo, yet nothing to send */
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spi->last_tx = 1; /* setting last_tx indicates TX is done */
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}
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while (f_tx) {
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if (spi->tx_buf && spi->tx_buf_len > 0) {
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switch (spi->dfs) {
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case 1:
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data = UNALIGNED_GET((u8_t *)(spi->tx_buf));
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break;
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case 2:
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data = UNALIGNED_GET((u16_t *)(spi->tx_buf));
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break;
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#ifndef CONFIG_ARC
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case 4:
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data = UNALIGNED_GET((u32_t *)(spi->tx_buf));
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break;
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#endif
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}
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spi->tx_buf += spi->dfs;
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spi->tx_buf_len--;
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} else if (spi->rx_buf && spi->rx_buf_len > 0) {
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/* No need to push more than necessary */
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if (spi->rx_buf_len - spi->fifo_diff <= 0) {
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break;
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}
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data = 0;
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} else {
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/* Nothing to push anymore */
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break;
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}
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write_dr(data, info->regs);
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f_tx--;
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spi->fifo_diff++;
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DBG_COUNTER_INC();
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}
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if (spi->last_tx) {
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write_txftlr(0, info->regs);
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/* prevents any further interrupts demanding TX fifo fill */
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}
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SYS_LOG_DBG("Pushed: %d", DBG_COUNTER_RESULT());
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}
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static void pull_data(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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u32_t data = 0;
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DBG_COUNTER_INIT();
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while (read_rxflr(info->regs)) {
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data = read_dr(info->regs);
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DBG_COUNTER_INC();
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if (spi->rx_buf && spi->rx_buf_len > 0) {
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switch (spi->dfs) {
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case 1:
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UNALIGNED_PUT(data, (u8_t *)spi->rx_buf);
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break;
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case 2:
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UNALIGNED_PUT(data, (u16_t *)spi->rx_buf);
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break;
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#ifndef CONFIG_ARC
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case 4:
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UNALIGNED_PUT(data, (u32_t *)spi->rx_buf);
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break;
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#endif
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}
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spi->rx_buf += spi->dfs;
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spi->rx_buf_len--;
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}
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spi->fifo_diff--;
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}
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if (!spi->rx_buf_len && spi->tx_buf_len < DW_SPI_FIFO_DEPTH) {
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write_rxftlr(spi->tx_buf_len - 1, info->regs);
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} else if (read_rxftlr(info->regs) >= spi->rx_buf_len) {
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write_rxftlr(spi->rx_buf_len - 1, info->regs);
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}
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SYS_LOG_DBG("Pulled: %d", DBG_COUNTER_RESULT());
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}
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static inline bool _spi_dw_is_controller_ready(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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if (test_bit_ssienr(info->regs) || test_bit_sr_busy(info->regs)) {
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return false;
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}
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return true;
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}
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static int spi_dw_configure(struct device *dev,
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struct spi_config *config)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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u32_t flags = config->config;
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u32_t ctrlr0 = 0;
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u32_t mode;
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SYS_LOG_DBG("%p (0x%x), %p", dev, info->regs, config);
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/* Check status */
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if (!_spi_dw_is_controller_ready(dev)) {
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SYS_LOG_DBG("Controller is busy");
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return -EBUSY;
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}
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/* Word size */
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ctrlr0 |= DW_SPI_CTRLR0_DFS(SPI_WORD_SIZE_GET(flags));
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/* Determine how many bytes are required per-frame */
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spi->dfs = SPI_WS_TO_DFS(SPI_WORD_SIZE_GET(flags));
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/* SPI mode */
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mode = SPI_MODE(flags);
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if (mode & SPI_MODE_CPOL) {
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ctrlr0 |= DW_SPI_CTRLR0_SCPOL;
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}
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if (mode & SPI_MODE_CPHA) {
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ctrlr0 |= DW_SPI_CTRLR0_SCPH;
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}
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if (mode & SPI_MODE_LOOP) {
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ctrlr0 |= DW_SPI_CTRLR0_SRL;
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}
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/* Installing the configuration */
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write_ctrlr0(ctrlr0, info->regs);
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/*
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* Configure the rate. Use this small hack to allow the user to call
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* spi_configure() with both a divider (as the driver was initially
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* written) and a frequency (as the SPI API suggests to). The clock
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* divider is a 16bit value, hence we can fairly, and safely, assume
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* that everything above this value is a frequency. The trade-off is
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* that if one wants to use a bus frequency of 64kHz (or less), it has
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* the use a divider...
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*/
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if (config->max_sys_freq > 0xffff) {
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write_baudr(SPI_DW_CLK_DIVIDER(config->max_sys_freq),
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info->regs);
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} else {
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write_baudr(config->max_sys_freq, info->regs);
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}
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return 0;
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}
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static int spi_dw_slave_select(struct device *dev, u32_t slave)
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{
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struct spi_dw_data *spi = dev->driver_data;
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SYS_LOG_DBG("%p %d", dev, slave);
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if (slave == 0 || slave > 16) {
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return -EINVAL;
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}
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spi->slave = 1 << (slave - 1);
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return 0;
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}
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static int spi_dw_transceive(struct device *dev,
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const void *tx_buf, u32_t tx_buf_len,
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void *rx_buf, u32_t rx_buf_len)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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u32_t rx_thsld = DW_SPI_RXFTLR_DFLT;
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u32_t imask;
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SYS_LOG_DBG("%p, %p, %u, %p, %u",
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dev, tx_buf, tx_buf_len, rx_buf, rx_buf_len);
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/* Check status */
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if (!_spi_dw_is_controller_ready(dev)) {
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SYS_LOG_DBG("Controller is busy");
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return -EBUSY;
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}
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/* Set buffers info */
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spi->tx_buf = tx_buf;
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spi->tx_buf_len = tx_buf_len/spi->dfs;
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spi->rx_buf = rx_buf;
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if (rx_buf) {
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spi->rx_buf_len = rx_buf_len/spi->dfs;
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} else {
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spi->rx_buf_len = 0; /* must be zero if no buffer */
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}
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spi->fifo_diff = 0;
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spi->last_tx = 0;
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/* Tx Threshold */
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write_txftlr(DW_SPI_TXFTLR_DFLT, info->regs);
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/* Does Rx thresholds needs to be lower? */
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if (spi->rx_buf_len && spi->rx_buf_len < DW_SPI_FIFO_DEPTH) {
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rx_thsld = spi->rx_buf_len - 1;
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} else if (!spi->rx_buf_len && spi->tx_buf_len < DW_SPI_FIFO_DEPTH) {
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rx_thsld = spi->tx_buf_len - 1;
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/* TODO: why? */
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}
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write_rxftlr(rx_thsld, info->regs);
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/* Slave select */
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write_ser(spi->slave, info->regs);
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_spi_control_cs(dev, 1);
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/* Enable interrupts */
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imask = DW_SPI_IMR_UNMASK;
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if (!rx_buf) {
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/* if there is no rx buffer, keep all rx interrupts masked */
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imask &= DW_SPI_IMR_MASK_RX;
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}
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write_imr(imask, info->regs);
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/* Enable the controller */
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set_bit_ssienr(info->regs);
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k_sem_take(&spi->device_sync_sem, K_FOREVER);
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if (spi->error) {
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spi->error = 0;
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return -EIO;
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}
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return 0;
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}
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void spi_dw_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct spi_dw_config *info = dev->config->config_info;
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u32_t error = 0;
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u32_t int_status;
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int_status = read_isr(info->regs);
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SYS_LOG_DBG("SPI int_status 0x%x - (tx: %d, rx: %d)",
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int_status, read_txflr(info->regs), read_rxflr(info->regs));
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if (int_status & DW_SPI_ISR_ERRORS_MASK) {
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error = 1;
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goto out;
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}
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if (int_status & DW_SPI_ISR_RXFIS) {
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pull_data(dev);
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}
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if (int_status & DW_SPI_ISR_TXEIS) {
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push_data(dev);
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}
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out:
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clear_interrupts(info->regs);
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completed(dev, error);
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}
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static const struct spi_driver_api dw_spi_api = {
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.configure = spi_dw_configure,
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.slave_select = spi_dw_slave_select,
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.transceive = spi_dw_transceive,
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};
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int spi_dw_init(struct device *dev)
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{
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const struct spi_dw_config *info = dev->config->config_info;
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struct spi_dw_data *spi = dev->driver_data;
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_clock_config(dev);
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_clock_on(dev);
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info->config_func();
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k_sem_init(&spi->device_sync_sem, 0, UINT_MAX);
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_spi_config_cs(dev);
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/* Masking interrupt and making sure controller is disabled */
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write_imr(DW_SPI_IMR_MASK, info->regs);
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clear_bit_ssienr(info->regs);
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SYS_LOG_DBG("Designware SPI driver initialized on device: %p", dev);
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return 0;
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}
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#ifdef CONFIG_SPI_0
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void spi_config_0_irq(void);
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struct spi_dw_data spi_dw_data_port_0;
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const struct spi_dw_config spi_dw_config_0 = {
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.regs = SPI_DW_PORT_0_REGS,
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_SPI_0_CLOCK_GATE_SUBSYS),
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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#ifdef CONFIG_SPI_DW_CS_GPIO
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.cs_gpio_name = CONFIG_SPI_0_CS_GPIO_PORT,
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.cs_gpio_pin = CONFIG_SPI_0_CS_GPIO_PIN,
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#endif
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.config_func = spi_config_0_irq
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};
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DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init,
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&spi_dw_data_port_0, &spi_dw_config_0,
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
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&dw_spi_api);
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void spi_config_0_irq(void)
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{
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#ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(SPI_DW_PORT_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
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irq_enable(SPI_DW_PORT_0_IRQ);
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_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
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#else /* SPI_DW_INTERRUPT_SEPARATED_LINES */
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IRQ_CONNECT(IRQ_SPI0_RX_AVAIL, CONFIG_SPI_0_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI0_TX_REQ, CONFIG_SPI_0_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI0_ERR_INT, CONFIG_SPI_0_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS);
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irq_enable(IRQ_SPI0_RX_AVAIL);
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irq_enable(IRQ_SPI0_TX_REQ);
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irq_enable(IRQ_SPI0_ERR_INT);
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_spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK);
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#endif
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}
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#endif /* CONFIG_SPI_0 */
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#ifdef CONFIG_SPI_1
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void spi_config_1_irq(void);
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struct spi_dw_data spi_dw_data_port_1;
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static const struct spi_dw_config spi_dw_config_1 = {
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.regs = SPI_DW_PORT_1_REGS,
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#ifdef CONFIG_SPI_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_SPI_1_CLOCK_GATE_SUBSYS),
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#endif /* CONFIG_SPI_DW_CLOCK_GATE */
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#ifdef CONFIG_SPI_DW_CS_GPIO
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.cs_gpio_name = CONFIG_SPI_1_CS_GPIO_PORT,
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.cs_gpio_pin = CONFIG_SPI_1_CS_GPIO_PIN,
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#endif
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.config_func = spi_config_1_irq
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};
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DEVICE_AND_API_INIT(spi_dw_port_1, CONFIG_SPI_1_NAME, spi_dw_init,
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&spi_dw_data_port_1, &spi_dw_config_1,
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
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&dw_spi_api);
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void spi_config_1_irq(void)
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{
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#ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(SPI_DW_PORT_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
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irq_enable(SPI_DW_PORT_1_IRQ);
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_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
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#else /* SPI_DW_INTERRUPT_SEPARATED_LINES */
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IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_1_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_1_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
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IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_1_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS);
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irq_enable(IRQ_SPI1_RX_AVAIL);
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irq_enable(IRQ_SPI1_TX_REQ);
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irq_enable(IRQ_SPI1_ERR_INT);
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_spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK);
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_spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK);
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#endif
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}
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#endif /* CONFIG_SPI_1 */
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