447 lines
12 KiB
C
447 lines
12 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <kernel.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <dma.h>
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#include "qm_dma.h"
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#include "qm_isr.h"
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#include "clk.h"
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#define CYCLE_NOP \
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__asm__ __volatile__ ("nop"); \
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__asm__ __volatile__ ("nop"); \
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__asm__ __volatile__ ("nop"); \
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__asm__ __volatile__ ("nop")
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struct dma_qmsi_config_info {
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qm_dma_t instance; /* Controller instance. */
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};
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struct dma_qmsi_context {
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u32_t index;
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struct device *dev;
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};
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struct dma_qmsi_driver_data {
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void (*transfer[QM_DMA_CHANNEL_NUM])(struct device *dev, void *data);
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void (*error[QM_DMA_CHANNEL_NUM])(struct device *dev, void *data);
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void *callback_data[QM_DMA_CHANNEL_NUM];
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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qm_dma_context_t saved_ctx;
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#endif
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void (*dma_user_callback[QM_DMA_CHANNEL_NUM])(struct device *dev,
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u32_t channel_id,
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int error_code);
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};
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static struct dma_qmsi_context dma_context[QM_DMA_CHANNEL_NUM];
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static void dma_qmsi_config(struct device *dev);
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static void dma_callback(void *callback_context, u32_t len,
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int error_code)
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{
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struct dma_qmsi_driver_data *data;
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u32_t channel;
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struct dma_qmsi_context *context = callback_context;
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channel = context->index;
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data = context->dev->driver_data;
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if (error_code != 0) {
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data->error[channel](context->dev,
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data->callback_data[channel]);
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return;
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}
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data->transfer[channel](context->dev, data->callback_data[channel]);
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}
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static void dma_drv_callback(void *callback_context, u32_t len,
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int error_code)
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{
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struct dma_qmsi_context *context = callback_context;
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struct dma_qmsi_driver_data *data;
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u32_t channel;
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channel = context->index;
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data = context->dev->driver_data;
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data->dma_user_callback[channel](context->dev, channel, error_code);
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}
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static int dma_qmsi_channel_config(struct device *dev, u32_t channel,
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struct dma_channel_config *config)
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{
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qm_dma_channel_config_t qmsi_cfg;
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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struct dma_qmsi_driver_data *data = dev->driver_data;
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qmsi_cfg.handshake_interface = (qm_dma_handshake_interface_t)
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config->handshake_interface;
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qmsi_cfg.handshake_polarity = (qm_dma_handshake_polarity_t)
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config->handshake_polarity;
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qmsi_cfg.source_transfer_width = (qm_dma_transfer_width_t)
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config->source_transfer_width;
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qmsi_cfg.channel_direction = (qm_dma_channel_direction_t)
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config->channel_direction;
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qmsi_cfg.destination_burst_length = (qm_dma_burst_length_t)
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config->destination_burst_length;
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qmsi_cfg.destination_transfer_width = (qm_dma_transfer_width_t)
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config->destination_transfer_width;
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qmsi_cfg.source_burst_length = (qm_dma_burst_length_t)
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config->source_burst_length;
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/* TODO: add support for using other DMA transfer types. */
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qmsi_cfg.transfer_type = QM_DMA_TYPE_SINGLE;
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data->callback_data[channel] = config->callback_data;
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data->transfer[channel] = config->dma_transfer;
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data->error[channel] = config->dma_error;
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dma_context[channel].index = channel;
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dma_context[channel].dev = dev;
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qmsi_cfg.callback_context = &dma_context[channel];
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qmsi_cfg.client_callback = dma_callback;
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return qm_dma_channel_set_config(info->instance, channel, &qmsi_cfg);
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}
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static int dma_qmsi_transfer_config(struct device *dev, u32_t channel,
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struct dma_transfer_config *config)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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return qm_dma_transfer_set_config(info->instance, channel,
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(qm_dma_transfer_t *)config);
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}
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static int width_index(u32_t num_bytes, u32_t *index)
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{
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switch (num_bytes) {
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case 1:
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*index = QM_DMA_TRANS_WIDTH_8;
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break;
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case 2:
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*index = QM_DMA_TRANS_WIDTH_16;
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break;
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case 4:
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*index = QM_DMA_TRANS_WIDTH_32;
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break;
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case 8:
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*index = QM_DMA_TRANS_WIDTH_64;
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break;
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case 16:
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*index = QM_DMA_TRANS_WIDTH_128;
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break;
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case 32:
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*index = QM_DMA_TRANS_WIDTH_256;
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int bst_index(u32_t num_units, u32_t *index)
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{
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switch (num_units) {
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case 1:
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*index = QM_DMA_BURST_TRANS_LENGTH_1;
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break;
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case 4:
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*index = QM_DMA_BURST_TRANS_LENGTH_4;
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break;
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case 8:
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*index = QM_DMA_BURST_TRANS_LENGTH_8;
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break;
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case 16:
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*index = QM_DMA_BURST_TRANS_LENGTH_16;
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break;
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case 32:
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*index = QM_DMA_BURST_TRANS_LENGTH_32;
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break;
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case 64:
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*index = QM_DMA_BURST_TRANS_LENGTH_64;
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break;
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case 128:
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*index = QM_DMA_BURST_TRANS_LENGTH_128;
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break;
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case 256:
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*index = QM_DMA_BURST_TRANS_LENGTH_256;
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int dma_qmsi_chan_config(struct device *dev, u32_t channel,
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struct dma_config *config)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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struct dma_qmsi_driver_data *data = dev->driver_data;
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qm_dma_transfer_t qmsi_transfer_cfg = { 0 };
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qm_dma_channel_config_t qmsi_cfg = { 0 };
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u32_t temp = 0;
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int ret = 0;
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if (config->block_count != 1) {
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return -ENOTSUP;
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}
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qmsi_cfg.handshake_interface = (qm_dma_handshake_interface_t)
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config->dma_slot;
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qmsi_cfg.channel_direction = (qm_dma_channel_direction_t)
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config->channel_direction;
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ret = width_index(config->source_data_size, &temp);
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if (ret != 0) {
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return ret;
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}
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qmsi_cfg.source_transfer_width = (qm_dma_transfer_width_t) temp;
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ret = width_index(config->dest_data_size, &temp);
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if (ret != 0) {
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return ret;
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}
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qmsi_cfg.destination_transfer_width = (qm_dma_transfer_width_t) temp;
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ret = bst_index(config->dest_burst_length, &temp);
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if (ret != 0) {
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return ret;
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}
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qmsi_cfg.destination_burst_length = (qm_dma_burst_length_t) temp;
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ret = bst_index(config->source_burst_length, &temp);
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if (ret != 0) {
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return ret;
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}
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qmsi_cfg.source_burst_length = (qm_dma_burst_length_t) temp;
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/* TODO: add support for using other DMA transfer types. */
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qmsi_cfg.transfer_type = QM_DMA_TYPE_SINGLE;
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data->dma_user_callback[channel] = config->dma_callback;
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dma_context[channel].index = channel;
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dma_context[channel].dev = dev;
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qmsi_cfg.callback_context = &dma_context[channel];
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qmsi_cfg.client_callback = dma_drv_callback;
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ret = qm_dma_channel_set_config(info->instance, channel, &qmsi_cfg);
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if (ret != 0) {
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return ret;
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}
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qmsi_transfer_cfg.block_size = config->head_block->block_size;
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qmsi_transfer_cfg.source_address = (u32_t *)
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config->head_block->source_address;
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qmsi_transfer_cfg.destination_address = (u32_t *)
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config->head_block->dest_address;
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return qm_dma_transfer_set_config(info->instance, channel,
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&qmsi_transfer_cfg);
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}
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static int dma_qmsi_transfer_start(struct device *dev, u32_t channel)
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{
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int ret;
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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ret = qm_dma_transfer_start(info->instance, channel);
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CYCLE_NOP;
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return ret;
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}
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static int dma_qmsi_start(struct device *dev, u32_t channel)
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{
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int ret;
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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ret = qm_dma_transfer_start(info->instance, channel);
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CYCLE_NOP;
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return ret;
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}
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static int dma_qmsi_transfer_stop(struct device *dev, u32_t channel)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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return qm_dma_transfer_terminate(info->instance, channel);
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}
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static int dma_qmsi_stop(struct device *dev, u32_t channel)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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return qm_dma_transfer_terminate(info->instance, channel);
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}
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static const struct dma_driver_api dma_funcs = {
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.channel_config = dma_qmsi_channel_config,
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.transfer_config = dma_qmsi_transfer_config,
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.transfer_start = dma_qmsi_transfer_start,
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.transfer_stop = dma_qmsi_transfer_stop,
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.config = dma_qmsi_chan_config,
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.start = dma_qmsi_start,
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.stop = dma_qmsi_stop
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void dma_qmsi_set_power_state(struct device *dev, u32_t power_state)
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{
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struct dma_qmsi_driver_data *ctx = dev->driver_data;
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ctx->device_power_state = power_state;
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}
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static u32_t dma_qmsi_get_power_state(struct device *dev)
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{
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struct dma_qmsi_driver_data *ctx = dev->driver_data;
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return ctx->device_power_state;
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}
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#else
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#define dma_qmsi_set_power_state(...)
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#endif
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int dma_qmsi_init(struct device *dev)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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dma_qmsi_config(dev);
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qm_dma_init(info->instance);
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dma_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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static const struct dma_qmsi_config_info dma_qmsi_config_data = {
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.instance = QM_DMA_0,
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};
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static struct dma_qmsi_driver_data dma_qmsi_dev_data;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static int dma_suspend_device(struct device *dev)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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struct dma_qmsi_driver_data *ctx = dev->driver_data;
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qm_dma_save_context(info->instance, &ctx->saved_ctx);
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dma_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int dma_resume_device(struct device *dev)
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{
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const struct dma_qmsi_config_info *info = dev->config->config_info;
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struct dma_qmsi_driver_data *ctx = dev->driver_data;
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qm_dma_restore_context(info->instance, &ctx->saved_ctx);
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dma_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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static int dma_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return dma_suspend_device(dev);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return dma_resume_device(dev);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = dma_qmsi_get_power_state(dev);
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}
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return 0;
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}
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#endif
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DEVICE_DEFINE(dma_qmsi, CONFIG_DMA_0_NAME, &dma_qmsi_init, dma_qmsi_device_ctrl,
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&dma_qmsi_dev_data, &dma_qmsi_config_data, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&dma_funcs);
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static void dma_qmsi_config(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_0, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_0_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_1, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_1_mask);
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#if (CONFIG_SOC_QUARK_SE_C1000)
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_2, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_2_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_3, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_3_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_4, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_4_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_5, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_5_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_6, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_6_mask);
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7), CONFIG_DMA_0_IRQ_PRI,
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qm_dma_0_isr_7, DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7));
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QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_7_mask);
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#endif /* CONFIG_SOC_QUARK_SE_C1000 */
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT),
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CONFIG_DMA_0_IRQ_PRI, qm_dma_0_error_isr,
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DEVICE_GET(dma_qmsi), 0);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT));
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#if (QM_LAKEMONT)
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QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_HOST_MASK;
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#elif (QM_SENSOR)
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QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_SS_MASK;
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#endif
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}
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