zephyr/dts/riscv32
Kumar Gala 0bed1007ed dts: cleanup missing #{address,size}-cells
A few i2c and spi bus nodes were missing #address-cells and #size-cells
properties.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-06-20 22:48:57 -05:00
..
microsemi-miv.dtsi dts: riscv32: microsemi-miv: add flash and sram 2019-05-10 10:34:31 -05:00
riscv32-fe310.dtsi dts: cleanup missing #{address,size}-cells 2019-06-20 22:48:57 -05:00
riscv32-litex-vexriscv.dtsi soc: riscv32: add LiteX VexRiscV SoC 2019-05-15 12:52:16 -05:00
rv32m1.dtsi dts: riscv32: update flash controller compatibility property 2019-06-03 10:43:47 -05:00
rv32m1_ri5cy.dtsi soc: riscv32: Move rv32m1 flash memory definitions to dts 2019-05-06 19:09:59 -04:00
rv32m1_zero_riscy.dtsi soc: riscv32: Move rv32m1 flash memory definitions to dts 2019-05-06 19:09:59 -04:00