Andy Ross ae4f7a1a06 arch/xtensa: Remember to spill windows in arch_cohere_stacks() ... When we reach this code in interrupt context, our upper GPRs contain a cross-stack call that may still include some registers from the interrupted thread. Those need to go out to memory before we can do our cache coherence dance here. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-03-08 11:14:27 -05:00
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include	…
offsets	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
startup	license: add missing SPDX headers	2021-02-11 08:05:16 -05:00
CMakeLists.txt	arch/xtensa: Inline atomics	2021-03-08 11:14:27 -05:00
README-WINDOWS.rst	arch/xtensa: Add an arch-internal README on register windows	2021-03-08 11:14:27 -05:00
cpu_idle.c	…
crt1.S	arch/xtensa: soc/intel_adsp: Rework MP code entry	2021-03-08 11:14:27 -05:00
debug_helpers_asm.S	…
fatal.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
irq_manage.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
irq_offload.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
tls.c	…
window_vectors.S	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
xtensa-asm2-util.S	arch/xtensa: Remember to spill windows in arch_cohere_stacks()	2021-03-08 11:14:27 -05:00
xtensa-asm2.c	arch/xtensa: Invalidate bottom of outbound stacks	2021-03-08 11:14:27 -05:00
xtensa_backtrace.c	…
xtensa_intgen.tmpl	…