38 lines
800 B
C
38 lines
800 B
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_POWER_H_
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#define _SOC_POWER_H_
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#include <power/power.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Bit 0 from GP0 register is used internally by the kernel
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* to handle PM multicore support. Any change on QMSI and/or
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* bootloader which affects this bit should take it in
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* consideration.
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*/
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#define GP0_BIT_SLEEP_READY BIT(0)
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/*
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* Power state map:
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* SYS_POWER_STATE_SLEEP_1: SS1 state with Timer ON
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* SYS_POWER_STATE_SLEEP_2: SS1 state with Timer ON
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* SYS_POWER_STATE_DEEP_SLEEP_1: SS2 with LPSS enabled state
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* SYS_POWER_STATE_DEEP_SLEEP_2: SLEEP state
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* SYS_POWER_STATE_DEEP_SLEEP_3: SLEEP state with LPMODE enabled
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_POWER_H_ */
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