165 lines
4.5 KiB
C
165 lines
4.5 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __POWER_STATES_H__
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#define __POWER_STATES_H__
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#include "qm_common.h"
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#include "qm_soc_regs.h"
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/**
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* SoC Power mode control for Quark SE Microcontrollers.
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*
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* Available SoC states are:
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* - Low Power Sensing Standby (LPSS)
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* - Sleep
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*
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* LPSS can only be enabled from the Sensor core,
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* refer to @ref ss_power_soc_lpss_enable for further details.
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*
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* @defgroup groupSoCPower Quark SE SoC Power states
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* @{
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*/
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/**
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* Enter SoC sleep state.
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*
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* Put the SoC into sleep state until next SoC wake event.
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*
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* - Core well is turned off
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* - Always on well is on
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* - Hybrid Clock is off
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* - RTC Clock is on
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*
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* Possible SoC wake events are:
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* - Low Power Comparator Interrupt
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* - AON GPIO Interrupt
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* - AON Timer Interrupt
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* - RTC Interrupt
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*/
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void power_soc_sleep(void);
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/**
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* Enter SoC deep sleep state.
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*
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* Put the SoC into deep sleep state until next SoC wake event.
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*
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* - Core well is turned off
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* - Always on well is on
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* - Hybrid Clock is off
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* - RTC Clock is on
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*
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* Possible SoC wake events are:
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* - Low Power Comparator Interrupt
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* - AON GPIO Interrupt
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* - AON Timer Interrupt
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* - RTC Interrupt
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*
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* This function puts 1P8V regulators and 3P3V into Linear Mode.
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*/
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void power_soc_deep_sleep(void);
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/**
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* @}
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*/
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#if (!QM_SENSOR)
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/**
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* Host Power mode control for Quark SE Microcontrollers.<BR>
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* These functions cannot be called from the Sensor Subsystem.
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*
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* @defgroup groupSEPower Quark SE Host Power states
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* @{
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*/
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/**
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* Enter Host C1 state.
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*
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* Put the Host into C1.<BR>
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* Processor Clock is gated in this state.<BR>
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* Nothing is turned off in this state.
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*
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* This function can be called with interrupts disabled.
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* Interrupts will be enabled before triggering the transition.
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*
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* A wake event causes the Host to transition to C0.<BR>
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* A wake event is a host interrupt.
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*/
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void power_cpu_c1(void);
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/**
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* Enter Host C2 state or SoC LPSS state.
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*
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* Put the Host into C2.
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* Processor Clock is gated in this state.
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* All rails are supplied.
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*
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* This enables entry in LPSS if:
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* - Sensor Subsystem is in SS2.
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* - LPSS entry is enabled.
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*
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* If C2 is entered:
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* - A wake event causes the Host to transition to C0.
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* - A wake event is a host interrupt.
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*
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* If LPSS is entered:
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* - LPSS wake events applies.
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* - If the Sensor Subsystem wakes the SoC from LPSS, Host is back in C2.
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*/
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void power_cpu_c2(void);
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/**
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* Enter Host C2LP state or SoC LPSS state.
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*
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* Put the Host into C2LP.
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* Processor Complex Clock is gated in this state.
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* All rails are supplied.
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*
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* This enables entry in LPSS if:
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* - Sensor Subsystem is in SS2.
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* - LPSS is allowed.
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*
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* If C2LP is entered:
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* - A wake event causes the Host to transition to C0.
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* - A wake event is a Host interrupt.
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*
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* If LPSS is entered:
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* - LPSS wake events apply if LPSS is entered.
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* - If the Sensor Subsystem wakes the SoC from LPSS,
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* Host transitions back to C2LP.
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*/
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void power_cpu_c2lp(void);
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#endif
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/**
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* @}
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*/
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#endif /* __POWER_STATES_H__ */
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