Charles E. Youse 3bc79fdf2c arch/x86: refactor APIC timer configuration to SoC level ... The APIC is part of the SoC, not the board, so move the defaults down. Signed-off-by: Charles E. Youse <charles.youse@intel.com>		2019-09-21 16:43:26 -07:00
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doc	docs: fix errors/ambiguities in docs for Apollo Lake boards	2019-09-04 10:02:25 +02:00
CMakeLists.txt	soc/x86/apollo_lake: architecture is goldmont	2019-09-15 11:33:47 +08:00
Kconfig.defconfig	arch/x86: refactor APIC timer configuration to SoC level	2019-09-21 16:43:26 -07:00
Kconfig.soc	soc/x86/apollo_lake: remove legacy PCI support	2019-06-01 10:00:32 -04:00
dts_fixup.h	dts: Convert from DT_<COMPAT>_<INSTANCE>_<PROP> to DT_INST...	2019-06-14 08:02:15 -05:00
linker.ld	arch/x86: complete 64-bit linker script	2019-09-15 11:33:47 +08:00
soc.c	drivers/timer/hpet.c: migrate to devicetree	2019-09-17 22:37:09 +08:00
soc.h	cleanup: include/: move misc/util.h to sys/util.h	2019-06-27 22:55:49 -04:00
soc_gpio.h	…