561 lines
12 KiB
Plaintext
561 lines
12 KiB
Plaintext
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2019 Centaur Analytics, Inc
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
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#include <zephyr/dt-bindings/power/stm32_pwr.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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cpu-power-states = <&stop0 &stop1 &stop2>;
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};
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power-states {
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stop0: state0 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <1>;
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min-residency-us = <500>;
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};
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stop1: state1 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <2>;
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min-residency-us = <700>;
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};
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stop2: state2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <3>;
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min-residency-us = <1000>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "st,stm32-msi-clock";
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msi-range = <6>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32l4-pll-clock";
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status = "disabled";
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};
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};
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mcos {
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mco1: mco1 {
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compatible = "st,stm32-clock-mco";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <4 0>;
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clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <8>;
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erase-block-size = <2048>;
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/* maximum erase time(ms) for a 2K sector */
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max-erase-time = <25>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@40010400 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x40010400 0x400>;
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num-lines = <16>;
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interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
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<10 0>, <23 0>, <40 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5-9", "line10-15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 5>, <10 6>;
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};
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pinctrl: pin-controller@48000000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x2000>;
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
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};
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gpioh: gpio@48001c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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interrupts = <37 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <38 0>;
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status = "disabled";
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};
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lpuart1: serial@40008000 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x40008000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
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resets = <&rctl STM32_RESET(APB1H, 0U)>;
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interrupts = <70 0>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c3: i2c@40005c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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quadspi: quadspi@a0001000 {
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compatible = "st,stm32-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa0001000 0x400>;
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interrupts = <71 0>;
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clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <35 5>;
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clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
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resets = <&rctl STM32_RESET(APB2, 11U)>;
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interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
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resets = <&rctl STM32_RESET(APB1L, 0U)>;
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interrupts = <28 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
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resets = <&rctl STM32_RESET(APB1L, 4U)>;
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interrupts = <54 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
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resets = <&rctl STM32_RESET(APB2, 16U)>;
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interrupts = <24 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
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resets = <&rctl STM32_RESET(APB2, 17U)>;
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interrupts = <25 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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interrupts = <41 0>;
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clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
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prescaler = <32768>;
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alarms-count = <2>;
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alrm-exti-line = <18>;
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status = "disabled";
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};
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adc1: adc@50040000 {
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compatible = "st,stm32-adc";
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reg = <0x50040000 0x100>;
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clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 7 13 25 48 93 248 641>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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adc2: adc@50040100 {
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compatible = "st,stm32-adc";
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reg = <0x50040100 0x100>;
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clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 7 13 25 48 93 248 641>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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dma1: dma@40020000 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020000 0x400>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
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dma-requests = <7>;
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status = "disabled";
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};
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dma2: dma@40020400 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020400 0x400>;
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interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
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clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
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dma-requests = <7>;
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status = "disabled";
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};
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
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interrupts = <65 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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lptim2: timers@40009400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
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interrupts = <66 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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rng: rng@50060800 {
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compatible = "st,stm32-rng";
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reg = <0x50060800 0x400>;
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interrupts = <80 0>;
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clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
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/* Following domain clock setting requires MSI
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* clock to be enabled with msi-range = <11>;
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*/
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<&rcc STM32_SRC_MSI CLK48_SEL(3)>;
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status = "disabled";
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};
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pwr: power@40007000 {
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compatible = "st,stm32-pwr";
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reg = <0x40007000 0x400>; /* PWR register bank */
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status = "disabled";
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wkup-pins-nb = <5>; /* 5 system wake-up pins */
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wkup-pins-pol;
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wkup-pins-pupd;
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#address-cells = <1>;
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#size-cells = <0>;
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wkup-pin@1 {
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reg = <0x1>;
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};
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wkup-pin@2 {
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reg = <0x2>;
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};
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wkup-pin@3 {
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reg = <0x3>;
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};
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wkup-pin@4 {
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reg = <0x4>;
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};
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|
|
|
wkup-pin@5 {
|
|
reg = <0x5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal";
|
|
ts-cal1-addr = <0x1FFF75A8>;
|
|
ts-cal2-addr = <0x1FFF75CA>;
|
|
ts-cal1-temp = <30>;
|
|
ts-cal2-temp = <130>;
|
|
ts-cal-vrefanalog = <3000>;
|
|
io-channels = <&adc1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vref: vref {
|
|
compatible = "st,stm32-vref";
|
|
vrefint-cal-addr = <0x1FFF75AA>;
|
|
vrefint-cal-mv = <3000>;
|
|
io-channels = <&adc1 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vbat: vbat {
|
|
compatible = "st,stm32-vbat";
|
|
ratio = <3>;
|
|
io-channels = <&adc1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smbus1: smbus1 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smbus3: smbus3 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|