167 lines
5.3 KiB
C
167 lines
5.3 KiB
C
/* board.h - board configuration macros for the generic arc BSP */
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/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This header file is used to specify and describe board-level aspects for the
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generic arc BSP.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
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/* address bases */
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#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
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#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
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#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
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#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
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#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
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#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
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#define PERIPH_ADDR_BASE_I2C_MST0 0x80012000 /* I2C Master 0 */
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#define PERIPH_ADDR_BASE_I2C_MST1 0x80012100 /* I2C Master 1 */
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#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
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#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
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#ifdef CONFIG_NSIM
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#define PERIPH_ADDR_BASE_UART0 0x4242 /* UART A */
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#else
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#define PERIPH_ADDR_BASE_UART0 0xB0002000 /* UART A */
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#define PERIPH_ADDR_BASE_UART1 0xB0002400 /* UART B */
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#endif
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/* IRQs */
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#define IRQ_TIMER0 16
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#define IRQ_TIMER1 17
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#define IRQ_I2C0_RX_AVAIL 18
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#define IRQ_I2C0_TX_REQ 19
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#define IRQ_I2C0_STOP_DET 20
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#define IRQ_I2C0_ERR 21
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#define IRQ_I2C1_RX_AVAIL 22
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#define IRQ_I2C1_TX_REQ 23
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#define IRQ_I2C1_STOP_DET 24
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#define IRQ_I2C1_ERR 25
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#define IRQ_SPI0_ERR_INT 26
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#define IRQ_SPI0_RX_AVAIL 27
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#define IRQ_SPI0_TX_REQ 28
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#define IRQ_SPI1_ERR_INT 29
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#define IRQ_SPI1_RX_AVAIL 30
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#define IRQ_SPI1_TX_REQ 31
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#define IRQ_ADC_IRQ 32
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#define IRQ_ADC_ERR 33
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#define IRQ_GPIO0_INTR 34
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#define IRQ_GPIO1_INTR 35
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#define IRQ_I2C_MST0_INTR 36
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#define IRQ_I2C_MST1_INTR 37
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#define IRQ_SPI_MST0_INTR 38
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#define IRQ_SPI_MST1_INTR 39
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#define IRQ_SPI_SLV_INTR 40
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#define IRQ_UART0_INTR 41
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#define IRQ_UART1_INTR 42
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#define IRQ_I2S_INTR 43
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#define IRQ_GPIO_INTR 44
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#define IRQ_PWM_TIMER_INTR 45
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#define IRQ_USB_INTR 46
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#define IRQ_RTC_INTR 47
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#define IRQ_WDOG_INTR 48
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#define IRQ_DMA_CHAN0 49
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#define IRQ_DMA_CHAN1 50
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#define IRQ_DMA_CHAN2 51
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#define IRQ_DMA_CHAN3 52
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#define IRQ_DMA_CHAN4 53
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#define IRQ_DMA_CHAN5 54
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#define IRQ_DMA_CHAN6 55
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#define IRQ_DMA_CHAN7 56
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#define IRQ_MAILBOXES_INTR 57
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#define IRQ_COMPARATORS_INTR 58
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#define IRQ_SYS_PMU_INTR 59
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#define IRQ_DMA_CHANS_ERR 60
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#define IRQ_INT_SRAM_CTLR 61
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#define IRQ_INT_FLASH0_CTLR 62
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#define IRQ_INT_FLASH1_CTLR 63
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#define IRQ_ALWAYS_ON_TMR 64
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#define IRQ_ADC_PWR 65
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#define IRQ_ADC_CALIB 66
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#define IRQ_ALWAYS_ON_GPIO 67
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#ifndef _ASMLANGUAGE
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#define EXC_FROM_IRQ(irq) ((irq) + 16)
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#define VECTOR_FROM_IRQ(irq) EXC_FROM_IRQ(irq)
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#define VECTOR_ADDR(vector) ((uint32_t *)((int)vector << 2))
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#include <misc/util.h>
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#include <drivers/rand32.h>
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/* ARCv2 timer 0 configuration settings for the system clock */
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#ifdef CONFIG_NANOKERNEL
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#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 32000000 /* 32MHz reference clock \
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*/
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#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
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#endif /* CONFIG_NANOKERNEL */
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#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
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#define CONFIG_ARCV2_TIMER0_INT_PRI 0
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#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
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#define CONFIG_ARCV2_TIMER1_INT_PRI 1
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/*
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* UART configuration settings
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*
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* This BSP only supports the nanokernel. Therefore:
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* - only polled mode is supported (interrupt-driven mode is NOT supported); and
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* - only the target console is supported (hostserver driver is NOT supported).
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*/
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#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
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#define CONFIG_UART_CONSOLE_BAUDRATE 115200
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#define CONFIG_UART_CONSOLE_REGS PERIPH_ADDR_BASE_UART0
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#define CONFIG_UART_CONSOLE_IRQ IRQ_UART0_INTR
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#define CONFIG_UART_CONSOLE_INT_PRI 0
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#define UART_REG_ADDR_INTERVAL 4 /* for ns16550 driver */
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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