26 lines
1005 B
Plaintext
26 lines
1005 B
Plaintext
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_LPC54114_M0)
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#else
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#endif
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#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS NXP_LPC_USART_40086000_BASE_ADDRESS
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#define CONFIG_USART_MCUX_LPC_0_BAUD_RATE NXP_LPC_USART_40086000_CURRENT_SPEED
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#define CONFIG_USART_MCUX_LPC_0_IRQ_PRI NXP_LPC_USART_40086000_IRQ_0_PRIORITY
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#define CONFIG_USART_MCUX_LPC_0_NAME NXP_LPC_USART_40086000_LABEL
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#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ NXP_LPC_MAILBOX_4008B000_IRQ_0
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#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY
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#define CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME NXP_LPC_MAILBOX_4008B000_LABEL
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#define CONFIG_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS NXP_LPC_MAILBOX_4008B000_BASE_ADDRESS
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/* End of SoC Level DTS fixup file */
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