99 lines
3.3 KiB
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99 lines
3.3 KiB
ReStructuredText
.. _opentitan_earlgrey:
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OpenTitan Earl Grey
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###################
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Overview
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********
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The OpenTitan Earl Grey chip is a low-power secure microcontroller that is
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designed for several use cases requiring hardware security. The `OpenTitan
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Github`_ page contains HDL code, utilities, and documentation relevant to the
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chip.
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Hardware
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********
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- RV32IMCB RISC-V "Ibex" core
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- 128kB main SRAM
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- Fixed-frequency and AON timers
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- 32 x GPIO
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- 4 x UART
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- 3 x I2C
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- 2 x SPI host
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- 1 x SPI device
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- Various security peripherals
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Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_.
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Supported Features
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==================
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The ``opentitan_earlgrey`` board configuration is designed and tested to run on
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the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| Timer | on-chip | RISC-V Machine Timer |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | SPI host |
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+-----------+------------+-------------------------------------+
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| WDT | on-chip | Always-On Timer (Watchdog) |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on Zephyr porting.
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Programming and Debugging
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*************************
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First, build and install Verilator as described in the `OpenTitan Verilator
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Setup`_ guide .
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Building and Flashing
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=====================
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Here is an example for building the :ref:`hello_world` application. The
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following steps were tested on OpenTitan master branch @ 6a3c2e98.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: opentitan_earlgrey
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:goals: build
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The OpenTitan Vchip_sim_tb tool can take the Zephyr .elf as input and place it
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in simulated flash. The OpenTitan test ROM will then run in simulation, read
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the manifest header from simulated flash, and begin executing Zephyr from the
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entry point.
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.. code-block:: console
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$OT_HOME/bazel-bin/hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verbose-mem-load \
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-r $OT_HOME/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.39.scr.vmem \
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--meminit=otp,$OT_HOME/bazel-out/k8-fastbuild/bin/hw/ip/otp_ctrl/data/img_rma.24.vmem \
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--meminit=flash,$ZEPHYR_PATH/build/zephyr/zephyr.elf
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UART output:
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.. code-block:: console
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I00000 test_rom.c:135] Version: earlgrey_silver_release_v5-9599-g6a3c2e988, Build Date: 2023-01-17 16:02:09
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I00001 test_rom.c:237] Test ROM complete, jumping to flash (addr: 20000384)!
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*** Booting Zephyr OS build zephyr-v3.2.0-3494-gf0729b494b98 ***
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Hello World! opentitan_earlgrey
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References
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**********
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.. target-notes::
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.. _OpenTitan Earl Grey Chip Datasheet: https://opentitan.org/book/hw/top_earlgrey/doc/specification.html
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.. _OpenTitan GitHub: https://github.com/lowRISC/opentitan
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.. _OpenTitan Verilator Setup: https://opentitan.org/guides/getting_started/setup_verilator.html
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