192 lines
6.6 KiB
ReStructuredText
192 lines
6.6 KiB
ReStructuredText
.. _litex-vexriscv:
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LiteX VexRiscv
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##############
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LiteX VexRiscv is an example of a system on a chip (SoC) that consists of
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a `VexRiscv processor <https://github.com/SpinalHDL/VexRiscv>`_
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and additional peripherals. This setup can be generated using
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`Zephyr on LiteX VexRiscv (reference platform)
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<https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
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or `LiteX SoC Builder <https://github.com/enjoy-digital/litex>`_
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and can be used on various FPGA chips.
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The bitstream (FPGA configuration file) can be obtained using both
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vendor-specific and open-source tools, including the
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`F4PGA toolchain <https://f4pga.org/>`_.
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The ``litex_vexriscv`` board configuration in Zephyr is meant for the
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LiteX VexRiscv SoC implementation generated for the
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`Digilent Arty A7-35T or A7-100T Development Boards
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<https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
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or `SDI-MIPI Video Converter <https://github.com/antmicro/sdi-mipi-video-converter>`_.
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.. image:: img/litex_vexriscv.jpg
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:align: center
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:alt: LiteX VexRiscv on Digilent Arty 35T Board
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LiteX is based on
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`Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
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and provides ready-made system components such as buses, streams, interconnects,
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common cores, and CPU wrappers to create SoCs easily. The tool contains
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mechanisms for integrating, simulating, and building various designs
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that target multiple chips of different vendors.
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More information about the LiteX project can be found on
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`LiteX's website <https://github.com/enjoy-digital/litex>`_.
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VexRiscv is a 32-bit implementation of the RISC-V CPU architecture
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written in the `SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_.
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The processor supports M, C, and A RISC-V instruction
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set extensions, with numerous optimizations that include multistage
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pipelines and data caching. The project provides many optional extensions
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that can be used to customize the design (JTAG, MMU, MUL/DIV extensions).
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The implementation is optimized for FPGA chips.
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More information about the project can be found on
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`VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
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To run the ZephyrOS on the VexRiscv CPU, it is necessary to prepare the
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bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achieved
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using the
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`Zephyr on LiteX VexRiscv <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
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reference platform. You can also use the official LiteX SoC Builder.
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Bitstream generation
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********************
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Zephyr on LiteX VexRiscv
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========================
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Using this platform ensures that all registers addresses are in the proper place.
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All drivers were tested using this platform.
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In order to generate the bitstream,
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proceed with the following instruction:
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1. Clone the repository and update all submodules:
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.. code-block:: bash
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git clone https://github.com/litex-hub/zephyr-on-litex-vexriscv.git
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cd zephyr-on-litex-vexriscv
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git submodule update --init --recursive
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Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. It can be done by following instructions in
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`this tutorial <https://f4pga-examples.readthedocs.io/en/latest/getting.html>`_.
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In order to generate the bitstream for the SDI-MIPI Video Converter, install
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oxide (yosys+nextpnr) toolchain by following
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`these instructions <https://github.com/gatecat/prjoxide#getting-started---complete-flow>`_.
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#. Next, get all required packages and run the install script:
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.. code-block:: bash
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apt-get install build-essential bzip2 python3 python3-dev python3-pip
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./install.sh
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#. Add LiteX to path:
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.. code-block:: bash
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source ./init
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#. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
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.. code-block:: bash
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export F4PGA_INSTALL_DIR=~/opt/f4pga
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export FPGA_FAM="xc7"
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export PATH="$F4PGA_INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
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source "$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh"
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conda activate $FPGA_FAM
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#. Generate the bitstream for the Arty 35T:
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.. code-block:: bash
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./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
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#. Generate the bitstream for the Arty 100T:
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.. code-block:: bash
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./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
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#. Generate the bitstream for the SDI-MIPI Video Converter:
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.. code-block:: bash
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./make.py --board=sdi_mipi_bridge --build --toolchain=oxide
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Official LiteX SoC builder
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==========================
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You can also generate the bitstream using the `official LiteX repository <https://github.com/enjoy-digital/litex>`_.
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In that case you must also generate a dts overlay.
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1. Install Migen/LiteX and the LiteX's cores:
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.. code-block:: bash
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wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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chmod +x litex_setup.py
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./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)
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#. Install the RISC-V toolchain:
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.. code-block:: bash
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pip3 install meson ninja
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./litex_setup.py --gcc=riscv
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#. Build the target:
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.. code-block:: bash
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./litex-boards/litex_boards/targets/digilent_arty.py --build --timer-uptime --csr-json csr.json
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#. Generate the dts and config overlay:
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.. code-block:: bash
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./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
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Programming and booting
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*************************
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Building
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========
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Applications for the ``litex_vexriscv`` board configuration can be built as usual
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(see :ref:`build_an_application`).
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In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
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to ``litex_vexriscv``.
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If you were generating bitstream with the official LiteX SoC builder you need to pass an additional argument:
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.. code-block:: bash
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west build -b litex_vexriscv path/to/app -DDTC_OVERLAY_FILE=path/to/overlay.dts
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Booting
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=======
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To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/xc3sprog>`_ or
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`openFPGALoader <https://github.com/trabucayre/openFPGALoader>`_:
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.. code-block:: bash
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xc3sprog -c nexys4 digilent_arty.bit
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.. code-block:: bash
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openFPGALoader -b arty_a7_100t digilent_arty.bit
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Use `ecpprog <https://github.com/gregdavill/ecpprog>`_ to upload the bitstream to SDI-MIPI Video Converter:
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.. code-block:: bash
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ecpprog -S antmicro_sdi_mipi_video_converter.bit
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You can boot from a serial port using litex_term (replace `ttyUSBX` with your device) , e.g.:
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.. code-block:: bash
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litex_term /dev/ttyUSBX --speed 115200 --kernel zephyr.bin
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