6de9fcf315
After some analysis I found out that there's no machine timer provided by the "riscv" vendor. There are some specs for the mtime/mtimecmp registers (this is why we can have a single driver), but the actual register layout or implementations differ amongst vendors. GD32 uses the Nuclei implementation, named "system timer" in their documentation. This patch aligns with vendor specs. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> |
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| .. | ||
| andes | ||
| espressif | ||
| gigadevice | ||
| ite | ||
| microsemi | ||
| openisa | ||
| sifive | ||
| starfive | ||
| telink | ||
| mpfs-icicle.dtsi | ||
| neorv32.dtsi | ||
| riscv32-litex-vexriscv.dtsi | ||
| virt.dtsi | ||