zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi

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/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <16>;
};
};
};
aliases {
flash-controller = &flash_controller;
rtc-0 = &rtc0;
rtc-1 = &rtc1;
uart-0 = &uart0;
uart-1 = &uart1;
adc-0 = &adc;
egu-0 = &egu0;
egu-1 = &egu1;
egu-2 = &egu2;
egu-3 = &egu3;
egu-4 = &egu4;
egu-5 = &egu5;
gpio-0 = &gpio0;
gpio-1 = &gpio1;
gpiote-0 = &gpiote;
i2c-0 = &i2c0;
i2c-1 = &i2c1;
ipc-0 = &ipc;
pdm-0 = &pdm0;
spi-0 = &spi0;
spi-1 = &spi1;
spi-2 = &spi2;
pwm-0 = &pwm0;
pwm-1 = &pwm1;
pwm-2 = &pwm2;
wdt-0 = &wdt;
timer-0 = &timer0;
timer-1 = &timer1;
timer-2 = &timer2;
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
};
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
/* Common nRF5340 Application MCU
* peripheral description
*/
#include "nrf5340_cpuapp_common.dtsi"
};
/* Additional Secure peripherals */
gpiote: gpiote@5000d000 {
compatible = "nordic,nrf-gpiote";
reg = <0x5000d000 0x1000>;
interrupts = <13 5>;
status = "disabled";
label = "GPIOTE_0";
};
spu: spu@50003000 {
compatible = "nordic,nrf-spu";
reg = <0x50003000 0x1000>;
interrupts = <3 1>;
status = "okay";
};
ficr: ficr@ff0000 {
compatible = "nordic,nrf-ficr";
reg = <0xff0000 0x1000>;
status = "okay";
};
uicr: uicr@ff8000 {
compatible = "nordic,nrf-uicr";
reg = <0xff8000 0x1000>;
status = "okay";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};