zephyr/arch
Carlo Caione 7a11d883cc riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL
Some early RISC-V SoCs have a problem when an `mret` instruction is used
outside a trap handler.

After the latest Zephyr RISC-V huge rework, the arch_switch code is
indeed calling `mret` when not in handler mode, breaking some early
RISC-V platforms.

Optionally restore the old behavior by adding a new
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL symbol.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-04 18:18:10 +02:00
..
arc arc: vector_table: Automatically place the IRQ vector table 2022-06-28 12:29:42 +02:00
arm modules: tfm: Allow enabling FPU in the application with TF-M enabled 2022-06-29 14:45:39 +00:00
arm64 arch/arm64: Enable 'large' code model for large targets 2022-07-04 15:42:53 +00:00
common irq: Fix IRQ vector table relocation 2022-06-28 12:29:42 +02:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix include: add more missing zephyr/ prefixes 2022-05-27 15:20:27 -07:00
riscv riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
sparc asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 coding guidelines: comply with MISRA C:2012 Rule 4.1 2022-06-30 19:51:59 -04:00
xtensa debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
CMakeLists.txt
Kconfig arch: Use a more sane ALIGN value 2022-06-28 12:29:42 +02:00