308 lines
5.5 KiB
Plaintext
308 lines
5.5 KiB
Plaintext
# Kconfig - FSL FRDM K64F platform configuration options
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#
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# Copyright (c) 2014-2016 Wind River Systems, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_FSL_FRDM_K64F
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config SOC
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default fsl_frdm_k64f
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config SRAM_BASE_ADDRESS
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default 0x20000000
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config FLASH_BASE_ADDRESS
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default 0x00000000
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config NUM_IRQ_PRIO_BITS
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int
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default 4
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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default 86
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 120000000
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config K64_CORE_CLOCK_DIVIDER
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int
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prompt "Freescale K64 core clock divider"
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default 1
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help
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This option specifies the divide value for the K64 processor core clock
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from the system clock.
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config K64_BUS_CLOCK_DIVIDER
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int
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prompt "Freescale K64 bus clock divider"
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default 2
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help
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This option specifies the divide value for the K64 bus clock from the
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system clock.
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config K64_FLEXBUS_CLOCK_DIVIDER
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int
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prompt "Freescale K64 FlexBus clock divider"
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default 3
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help
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This option specifies the divide value for the K64 FlexBus clock from the
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system clock.
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config K64_FLASH_CLOCK_DIVIDER
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int
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prompt "Freescale K64 flash clock divider"
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default 5
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help
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This option specifies the divide value for the K64 flash clock from the
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system clock.
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config WDOG_INIT
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def_bool y
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# omit prompt to signify a "hidden" option
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help
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This processor enables the watchdog timer with a short timeout
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upon reset. Therefore, this requires that the watchdog be configured
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during reset handling.
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config KERNEL_INIT_PRIORITY_DEFAULT
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default 40
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config KERNEL_INIT_PRIORITY_DEVICE
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default 50
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config UART_CONSOLE_PRIORITY
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default 60
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if UART_K20
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config UART_K20_PORT_0
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def_bool y
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if UART_K20_PORT_0
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config UART_K20_PORT_0_BASE_ADDR
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default 0x4006A000
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config UART_K20_PORT_0_IRQ
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default 31
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config UART_K20_PORT_0_IRQ_PRI
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default 3
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config UART_K20_PORT_0_BAUD_RATE
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default 115200
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config UART_K20_PORT_0_CLK_FREQ
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default 120000000
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endif
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config UART_K20_PORT_1
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def_bool y
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if UART_K20_PORT_1
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config UART_K20_PORT_1_BASE_ADDR
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default 0x4006B000
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config UART_K20_PORT_1_IRQ
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default 33
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config UART_K20_PORT_1_IRQ_PRI
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default 3
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config UART_K20_PORT_1_BAUD_RATE
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default 115200
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config UART_K20_PORT_1_CLK_FREQ
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default 120000000
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endif
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config UART_K20_PORT_2
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def_bool y
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if UART_K20_PORT_2
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config UART_K20_PORT_2_BASE_ADDR
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default 0x4006C000
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config UART_K20_PORT_2_IRQ
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default 35
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config UART_K20_PORT_2_IRQ_PRI
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default 3
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config UART_K20_PORT_2_BAUD_RATE
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default 115200
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config UART_K20_PORT_2_CLK_FREQ
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default 120000000
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endif
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config UART_K20_PORT_3
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def_bool y
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if UART_K20_PORT_3
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config UART_K20_PORT_3_BASE_ADDR
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default 0x4006D000
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config UART_K20_PORT_3_IRQ
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default 37
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config UART_K20_PORT_3_IRQ_PRI
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default 3
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config UART_K20_PORT_3_BAUD_RATE
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default 115200
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config UART_K20_PORT_3_CLK_FREQ
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default 120000000
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endif
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config UART_K20_PORT_4
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def_bool y
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if UART_K20_PORT_4
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config UART_K20_PORT_4_BASE_ADDR
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default 0x400EA000
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config UART_K20_PORT_4_IRQ
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default 66
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config UART_K20_PORT_4_IRQ_PRI
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default 3
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config UART_K20_PORT_4_BAUD_RATE
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default 115200
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config UART_K20_PORT_4_CLK_FREQ
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default 120000000
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endif
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endif # UART_K20
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if UART_CONSOLE
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config UART_CONSOLE_ON_DEV_NAME
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default "UART_0"
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endif
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if BLUETOOTH_UART
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config BLUETOOTH_UART_ON_DEV_NAME
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default "UART_1"
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endif
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config GPIO
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def_bool y
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config PINMUX
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def_bool y
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config PWM
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def_bool n
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if GPIO
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config GPIO_K64
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def_bool y
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config GPIO_K64_A
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def_bool y
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config GPIO_K64_B
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def_bool y
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config GPIO_K64_C
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def_bool y
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config GPIO_K64_D
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def_bool y
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config GPIO_K64_E
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def_bool y
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endif
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config GPIO_K64_A_BASE_ADDR
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default 0x400FF000
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config PORT_K64_A_BASE_ADDR
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default 0x40049000
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config GPIO_K64_B_BASE_ADDR
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default 0x400FF040
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config PORT_K64_B_BASE_ADDR
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default 0x4004A000
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config GPIO_K64_C_BASE_ADDR
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default 0x400FF080
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config PORT_K64_C_BASE_ADDR
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default 0x4004B000
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config GPIO_K64_D_BASE_ADDR
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default 0x400FF0C0
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config PORT_K64_D_BASE_ADDR
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default 0x4004C000
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config GPIO_K64_E_BASE_ADDR
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default 0x400FF100
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config PORT_K64_E_BASE_ADDR
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default 0x4004D000
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if PINMUX
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config PINMUX_K64
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def_bool y
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config PINMUX_BASE
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default 0x00000000
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config PINMUX_NUM_PINS
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default 160
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config PINMUX_K64_GPIO_A_NAME
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default GPIO_K64_A_DEV_NAME
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config PINMUX_K64_GPIO_B_NAME
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default GPIO_K64_B_DEV_NAME
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config PINMUX_K64_GPIO_C_NAME
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default GPIO_K64_C_DEV_NAME
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config PINMUX_K64_GPIO_D_NAME
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default GPIO_K64_D_DEV_NAME
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config PINMUX_K64_GPIO_E_NAME
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default GPIO_K64_E_DEV_NAME
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config PRESERVE_JTAG_IO_PINS
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bool "Freescale FRDM-K64F JTAG pin usage"
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depends on PINMUX
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default y
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help
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The FRDM-K64F board routes the PTA0/1/2 pins as JTAG/SWD signals that
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are used for the OpenSDAv2 debug interface. These pins are also routed to
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the Arduino header as D8, D3 and D5, respectively.
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Enable this option to preserve these pins for the debug interface.
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endif # PINMUX
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if PWM
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config PWM_K64_FTM
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def_bool y
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config PWM_K64_FTM_0
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def_bool y
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endif
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config SPI
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def_bool n
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if SPI
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config SPI_K64
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def_bool y
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config SPI_K64_0
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def_bool y
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config SPI_K64_1
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def_bool n
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config SPI_K64_2
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def_bool n
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endif
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endif # SOC_FSL_FRDM_K64F
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