zephyr/dts/riscv
Kumar Gala 2c1e0439c7 irq: rv32m1: Fixup IRQ values for multi-level IRQ handling
Remove the handcoded multi-level IRQ values in device tree.  We now are
able to generate the encoded multi-level IRQ value.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-10 07:34:57 -05:00
..
microsemi-miv.dtsi
riscv32-fe310.dtsi riscv: add a qemu_riscv64 board 2019-08-09 09:11:45 -05:00
riscv32-litex-vexriscv.dtsi
rv32m1.dtsi dts: rv32m1: Rework interrupt mux dts descriptions 2019-09-09 13:47:20 -05:00
rv32m1_ri5cy.dtsi irq: rv32m1: Fixup IRQ values for multi-level IRQ handling 2019-09-10 07:34:57 -05:00
rv32m1_zero_riscy.dtsi irq: rv32m1: Fixup IRQ values for multi-level IRQ handling 2019-09-10 07:34:57 -05:00