227 lines
6.1 KiB
C
227 lines
6.1 KiB
C
/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <xtensa-asm2.h>
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#include <kernel.h>
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#include <ksched.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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#include <kswap.h>
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#include <_soc_inthandlers.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(os);
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void *xtensa_init_stack(int *stack_top,
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void (*entry)(void *, void *, void *),
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void *arg1, void *arg2, void *arg3)
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{
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/* We cheat and shave 16 bytes off, the top four words are the
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* A0-A3 spill area for the caller of the entry function,
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* which doesn't exist. It will never be touched, so we
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* arrange to enter the function with a CALLINC of 1 and a
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* stack pointer 16 bytes above the top, so its ENTRY at the
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* start will decrement the stack pointer by 16.
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*/
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const int bsasz = BASE_SAVE_AREA_SIZE - 16;
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void **bsa = (void **) (((char *) stack_top) - bsasz);
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(void)memset(bsa, 0, bsasz);
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bsa[BSA_PC_OFF/4] = z_thread_entry;
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bsa[BSA_PS_OFF/4] = (void *)(PS_WOE | PS_UM | PS_CALLINC(1));
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/* Arguments to z_thread_entry(). Remember these start at A6,
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* which will be rotated into A2 by the ENTRY instruction that
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* begins the C function. And A4-A7 and A8-A11 are optional
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* quads that live below the BSA!
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*/
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bsa[-1] = arg1; /* a7 */
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bsa[-2] = entry; /* a6 */
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bsa[-3] = 0; /* a5 */
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bsa[-4] = 0; /* a4 */
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bsa[-5] = 0; /* a11 */
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bsa[-6] = 0; /* a10 */
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bsa[-7] = arg3; /* a9 */
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bsa[-8] = arg2; /* a8 */
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/* Finally push the BSA pointer and return the stack pointer
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* as the handle
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*/
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bsa[-9] = bsa;
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return &bsa[-9];
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}
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void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz,
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k_thread_entry_t entry, void *p1, void *p2, void *p3,
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int prio, unsigned int opts)
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{
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char *base = Z_THREAD_STACK_BUFFER(stack);
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char *top = base + sz;
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/* Align downward. The API as specified requires a runtime check. */
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top = (char *)(((unsigned int)top) & ~3);
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z_new_thread_init(thread, base, sz, prio, opts);
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thread->switch_handle = xtensa_init_stack((void *)top, entry,
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p1, p2, p3);
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}
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void z_irq_spurious(void *arg)
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{
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int irqs, ie;
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ARG_UNUSED(arg);
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__asm__ volatile("rsr.interrupt %0" : "=r"(irqs));
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__asm__ volatile("rsr.intenable %0" : "=r"(ie));
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LOG_ERR(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p",
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(void *)irqs, (void *)ie);
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z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
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}
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void z_xtensa_dump_stack(const z_arch_esf_t *stack)
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{
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int *bsa = *(int **)stack;
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LOG_ERR(" ** A0 %p SP %p A2 %p A3 %p",
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(void *)bsa[BSA_A0_OFF/4],
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((char *)bsa) + BASE_SAVE_AREA_SIZE,
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(void *)bsa[BSA_A2_OFF/4], (void *)bsa[BSA_A3_OFF/4]);
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if (bsa - stack > 4) {
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LOG_ERR(" ** A4 %p A5 %p A6 %p A7 %p",
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(void *)bsa[-4], (void *)bsa[-3],
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(void *)bsa[-2], (void *)bsa[-1]);
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}
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if (bsa - stack > 8) {
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LOG_ERR(" ** A8 %p A9 %p A10 %p A11 %p",
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(void *)bsa[-8], (void *)bsa[-7],
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(void *)bsa[-6], (void *)bsa[-5]);
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}
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if (bsa - stack > 12) {
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LOG_ERR(" ** A12 %p A13 %p A14 %p A15 %p",
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(void *)bsa[-12], (void *)bsa[-11],
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(void *)bsa[-10], (void *)bsa[-9]);
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}
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#if XCHAL_HAVE_LOOPS
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LOG_ERR(" ** LBEG %p LEND %p LCOUNT %p",
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(void *)bsa[BSA_LBEG_OFF/4],
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(void *)bsa[BSA_LEND_OFF/4],
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(void *)bsa[BSA_LCOUNT_OFF/4]);
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#endif
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LOG_ERR(" ** SAR %p", (void *)bsa[BSA_SAR_OFF/4]);
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}
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static inline unsigned int get_bits(int offset, int num_bits, unsigned int val)
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{
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int mask;
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mask = BIT(num_bits) - 1;
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val = val >> offset;
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return val & mask;
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}
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/* The wrapper code lives here instead of in the python script that
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* generates _xtensa_handle_one_int*(). Seems cleaner, still kind of
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* ugly.
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*/
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#define DEF_INT_C_HANDLER(l) \
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void *xtensa_int##l##_c(void *interrupted_stack) \
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{ \
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u32_t irqs, intenable, m; \
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__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
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__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
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irqs &= intenable; \
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while ((m = _xtensa_handle_one_int##l(irqs))) { \
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irqs ^= m; \
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__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
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} \
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return z_get_next_switch_handle(interrupted_stack); \
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}
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DEF_INT_C_HANDLER(2)
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DEF_INT_C_HANDLER(3)
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DEF_INT_C_HANDLER(4)
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DEF_INT_C_HANDLER(5)
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DEF_INT_C_HANDLER(6)
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DEF_INT_C_HANDLER(7)
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static inline DEF_INT_C_HANDLER(1)
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/* C handler for level 1 exceptions/interrupts. Hooked from the
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* DEF_EXCINT 1 vector declaration in assembly code. This one looks
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* different because exceptions and interrupts land at the same
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* vector; other interrupt levels have their own vectors.
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*/
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void *xtensa_excint1_c(int *interrupted_stack)
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{
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int cause, vaddr, *bsa = *(int **)interrupted_stack;
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__asm__ volatile("rsr.exccause %0" : "=r"(cause));
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if (cause == EXCCAUSE_LEVEL1_INTERRUPT) {
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return xtensa_int1_c(interrupted_stack);
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} else if (cause == EXCCAUSE_SYSCALL) {
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/* Just report it to the console for now */
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LOG_ERR(" ** SYSCALL PS %p PC %p",
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(void *)bsa[BSA_PS_OFF/4], (void *)bsa[BSA_PC_OFF/4]);
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z_xtensa_dump_stack(interrupted_stack);
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/* Xtensa exceptions don't automatically advance PC,
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* have to skip the SYSCALL instruction manually or
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* else it will just loop forever
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*/
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bsa[BSA_PC_OFF/4] += 3;
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} else {
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u32_t ps = bsa[BSA_PS_OFF/4];
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__asm__ volatile("rsr.excvaddr %0" : "=r"(vaddr));
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LOG_ERR(" ** FATAL EXCEPTION");
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LOG_ERR(" ** CPU %d EXCCAUSE %d (%s)",
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z_arch_curr_cpu()->id, cause,
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z_xtensa_exccause(cause));
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LOG_ERR(" ** PC %p VADDR %p",
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(void *)bsa[BSA_PC_OFF/4], (void *)vaddr);
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LOG_ERR(" ** PS %p", (void *)bsa[BSA_PS_OFF/4]);
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LOG_ERR(" ** (INTLEVEL:%d EXCM: %d UM:%d RING:%d WOE:%d OWB:%d CALLINC:%d)",
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get_bits(0, 4, ps), get_bits(4, 1, ps),
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get_bits(5, 1, ps), get_bits(6, 2, ps),
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get_bits(18, 1, ps),
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get_bits(8, 4, ps), get_bits(16, 2, ps));
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/* FIXME: legacy xtensa port reported "HW" exception
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* for all unhandled exceptions, which seems incorrect
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* as these are software errors. Should clean this
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* up.
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*/
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z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION,
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(void *)interrupted_stack);
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}
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return z_get_next_switch_handle(interrupted_stack);
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}
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int z_xtensa_irq_is_enabled(unsigned int irq)
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{
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u32_t ie;
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__asm__ volatile("rsr.intenable %0" : "=r"(ie));
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return (ie & (1 << irq)) != 0;
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}
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