333 lines
10 KiB
ReStructuredText
333 lines
10 KiB
ReStructuredText
.. _altera_max10:
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Altera MAX10
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############
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Overview
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********
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The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using
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the Nios II Gen 2 soft CPU.
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.. figure:: img/altera_max10.jpg
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:align: center
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:alt: Altera's MAX* 10
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Altera's MAX* 10 (Credit: Altera)
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Hardware
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********
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DIP Switch settings
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===================
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There are two sets of switches on the back of the board. Of particular
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importance is SW2:
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* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first
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boot image is CFM0
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* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing
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scripts won't work
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* Switch 4 (HSMC_BYPASSN) should be OFF (up)
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.. image:: img/Altera_MAX10_switches.jpg
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:align: center
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:alt: Altera's MAX* 10 Switches
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Other switches are user switches, their position is application-specific.
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Necessary Software
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==================
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You will need the Altera Quartus SDK in order to work with this device. The
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`Altera Lite Distribution`_ of Quartus may be obtained without
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charge.
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For your convenience using the SDK tools (such as ``nios2-configure-sof``),
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you should put the binaries provided by the SDK
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in your path. Below is an example, adjust ALTERA_BASE to where you installed the
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SDK:
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.. code-block:: console
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export ALTERA_BASE=/opt/altera_lite/16.0
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export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin
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You may need to adjust your udev rules so that you can talk to the USB Blaster
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II peripheral, which is the built-in JTAG interface for this device.
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The following works for Fedora 23:
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.. code-block:: console
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# For Altera USB-Blaster permissions.
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SUBSYSTEM=="usb",\
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ENV{DEVTYPE}=="usb_device",\
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ATTR{idVendor}=="09fb",\
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ATTR{idProduct}=="6010",\
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MODE="0666",\
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NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
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RUN+="/bin/chmod 0666 %c"
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SUBSYSTEM=="usb",\
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ENV{DEVTYPE}=="usb_device",\
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ATTR{idVendor}=="09fb",\
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ATTR{idProduct}=="6810",\
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MODE="0666",\
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NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
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RUN+="/bin/chmod 0666 %c"
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You can test connectivity with the SDK jtagconfig tool, you should see something
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like:
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.. code-block:: console
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$ jtagconfig
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1) USB-BlasterII [1-1.2]
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031050DD 10M50DA(.|ES)/10M50DC
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020D10DD VTAP10
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Reference CPU
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=============
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A reference CPU design of a Nios II/f core is included in the Zephyr tree
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in the :zephyr_file:`soc/nios2/nios2f-zephyr/cpu` directory.
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Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA
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configuration file
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:zephyr_file:`soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof`:
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.. code-block:: console
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$ nios2-configure-sof ghrd_10m50da.sof
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This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer.
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For any Nios II SOC definition, you can find out more details about the CPU
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configuration by inspecting system.h in the SOC's include directory.
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Console Output
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==============
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16550 UART
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----------
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By default, the kernel is configured to send console output to the 16550 UART.
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You can monitor this on your workstation by connecting to the top right mini USB
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port on the board (it will show up in /dev as a ttyUSB node), and then running
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minicom with flow control disabled, 115200-8N1 settings.
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JTAG UART
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---------
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You can also have it send its console output to the JTAG UART.
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Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file:
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.. code-block:: devicetree
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&jtag_uart {
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status = "okay";
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current-speed = <115200>;
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};
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To view these messages on your local workstation, run the terminal application
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in the SDK:
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.. code-block:: console
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$ nios2-terminal
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Programming and Debugging
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*************************
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Flashing
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========
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Flashing Kernel into UFM
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------------------------
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The usual ``flash`` target will work with the ``altera_max10`` board
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configuration. Here is an example for the :ref:`hello_world`
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application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: altera_max10
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:goals: flash
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Refer to :ref:`build_an_application` and :ref:`application_run` for
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more details.
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This provisions the Zephyr kernel and the CPU configuration onto the board,
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using the scripts/support/quartus-flash.py script. After it completes the kernel
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will immediately boot.
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Flashing Kernel directly into RAM over JTAG
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-------------------------------------------
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The SDK included the nios2-download tool which will let you flash a kernel
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directly into RAM and then boot it from the __start symbol.
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In order for this to work, your entire kernel must be located in RAM. Make sure
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the following config options are disabled:
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.. code-block:: console
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CONFIG_XIP=n
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CONFIG_INCLUDE_RESET_VECTOR=n
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Then, after building your kernel, push it into device's RAM by running
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this from the build directory:
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.. code-block:: console
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$ nios2-download --go zephyr/zephyr.elf
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If you have a console session running (either minicom or nios2-terminal) you
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should see the application's output. There are additional arguments you can pass
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to nios2-download so that it spawns a GDB server that you can connect to,
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although it's typically simpler to just use nios2-gdb-server as described below.
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Debugging
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=========
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The Altera SDK includes a GDB server which can be used to debug a MAX10 board.
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You can either debug a running image that was flashed onto the device in User
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Flash Memory (UFM), or load an image over the JTAG using GDB.
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Debugging With UFM Flashed Image
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--------------------------------
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You can debug an application in the usual way. Here is an example.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: altera_max10
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:goals: debug
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You will see output similar to the following:
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.. code-block:: console
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Nios II GDB server running on port 3335
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Ignoring --stop option because --tcpport also specified
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GNU gdb (GDB) 7.11.0.20160511-git
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Copyright (C) 2016 Free Software Foundation, Inc.
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License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
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This is free software: you are free to change and redistribute it.
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There is NO WARRANTY, to the extent permitted by law. Type "show copying"
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and "show warranty" for details.
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This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf".
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Type "show configuration" for configuration details.
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For bug reporting instructions, please see:
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<http://www.gnu.org/software/gdb/bugs/>.
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Find the GDB manual and other documentation resources online at:
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<http://www.gnu.org/software/gdb/documentation/>.
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For help, type "help".
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Type "apropos word" to search for commands related to "word"...
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Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done.
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Remote debugging using :3335
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Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00
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Resetting and pausing target processor: OK
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Listening on port 3335 for connection from GDB: accepted
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isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63
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63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list));
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(gdb) b z_prep_c
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Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36.
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(gdb) b z_cstart
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Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348.
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(gdb) c
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Continuing.
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Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348
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348 {
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(gdb)
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To start debugging manually:
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.. code-block:: console
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nios2-gdb-server --tcpport 1234 --stop --reset-target
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And then connect with GDB from the build directory:
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.. code-block:: console
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nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234"
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Debugging With JTAG Flashed Image
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---------------------------------
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In order for this to work, execute-in-place must be disabled, since the GDB
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'load' command can only put text and data in RAM. Ensure this is in your
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configuration:
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.. code-block:: console
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CONFIG_XIP=n
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It is OK for this procedure to leave the reset vector enabled, unlike
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nios2-download (which errors out if it finds sections outside of SRAM) it will
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be ignored.
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In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if
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any) is on the device, but you should have at least flashed a CPU using
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nios2-configure-sof. You can leave this process running.
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.. code-block:: console
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$ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target
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Build your Zephyr kernel, and load it into a GDB built for Nios II (included in
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the Zephyr SDK) from the build directory:
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.. code-block:: console
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$ nios2-poky-elf-gdb zephyr/zephyr.elf
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Then connect to the GDB server:
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.. code-block:: console
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(gdb) target remote :1234
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And then load the kernel image over the wire. The CPU will not start from the
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reset vector, instead it will boot from the __start symbol:
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.. code-block:: console
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(gdb) load
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Loading section reset, size 0xc lma 0x0
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Loading section exceptions, size 0x1b0 lma 0x400020
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Loading section text, size 0x8df0 lma 0x4001d0
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Loading section devconfig, size 0x30 lma 0x408fc0
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Loading section rodata, size 0x3f4 lma 0x408ff0
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Loading section datas, size 0x888 lma 0x4093e4
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Loading section initlevel, size 0x30 lma 0x409c6c
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Loading section _k_task_list, size 0x58 lma 0x409c9c
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Loading section _k_task_ptr, size 0x8 lma 0x409cf4
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Loading section _k_event_list, size 0x10 lma 0x409cfc
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Start address 0x408f54, load size 40184
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Transfer rate: 417 KB/sec, 368 bytes/write.
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After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again.
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References
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**********
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* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
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* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
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* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
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* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
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* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
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* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
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* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
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.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html
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