135 lines
4.0 KiB
C
135 lines
4.0 KiB
C
/*
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* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Board configuration macros for EM Starter kit board
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*
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* This header file is used to specify and describe board-level
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* aspects for the target.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
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/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
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/* IRQs */
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#define IRQ_TIMER0 16
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#define IRQ_TIMER1 17
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#ifndef _ASMLANGUAGE
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#include <misc/util.h>
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#include <drivers/rand32.h>
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#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
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#define CONFIG_ARCV2_TIMER0_INT_PRI 0
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#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
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#define CONFIG_ARCV2_TIMER1_INT_PRI 1
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#define INT_ENABLE_ARC ~(0x00000001 << 8)
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#define INT_ENABLE_ARC_BIT_POS (8)
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/* I2C */
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/* I2C_0 is on Pmod2 connector */
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#define I2C_DW_0_BASE_ADDR 0xF0004000
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#define I2C_DW_0_IRQ 23
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/* I2C_1 is on Pmod4 connector */
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#define I2C_DW_1_BASE_ADDR 0xF0005000
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#define I2C_DW_1_IRQ 24
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#define I2C_DW_IRQ_FLAGS 0
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/* GPIO */
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#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
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#define GPIO_DW_0_IRQ 22
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#define GPIO_DW_0_BITS 32
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#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
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#define GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
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#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
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#define GPIO_DW_1_IRQ 0 /* can't interrupt */
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#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
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#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
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#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
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#define GPIO_DW_2_IRQ 0 /* can't interrupt */
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#define GPIO_DW_2_BITS 32
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#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
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#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
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#define GPIO_DW_3_IRQ 0 /* can't interrupt */
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#define GPIO_DW_3_BITS 12
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#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
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/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
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/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
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/* undef CONFIG_GPIO_DW_CLOCK_GATE */
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/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
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/* SPI */
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#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
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#define SPI_DW_PORT_0_REGS 0xF0006000
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#define SPI_DW_PORT_1_REGS 0xF0007000
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#define SPI_DW_PORT_0_IRQ 25
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#define SPI_DW_PORT_1_IRQ 26
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#define SPI_DW_IRQ_FLAGS 0
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/*
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* SPI Chip Select Assignments on EM Starter Kit
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*
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* CS0 Pmod6 - pin 1 - J6
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* CS1 Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
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* CS2 Pmod6 - pin 8 - J6
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* CS3 SDCard (onboard)
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* CS4 Internal SPI Slave - loopback
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* CS5 SPI-Flash (onboard)
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*/
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/*
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* UART
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UART0 vector 27 0xF0008000
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UART1 vector 28 0xF0009000
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UART2 vector 29 0xF000A000
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*/
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#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
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#define UART_NS16550_PORT_0_IRQ 27
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#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
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#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
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#define UART_NS16550_PORT_1_IRQ 28
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#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
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#define UART_IRQ_FLAGS 0 /* Default */
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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