260 lines
3.6 KiB
Plaintext
260 lines
3.6 KiB
Plaintext
#
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# Copyright (c) 2014 Wind River Systems, Inc.
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# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_EM7D
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config SOC
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default em7d
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 4 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
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# TODO: But regular irq nesting is not implemented --
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# so this must be 2 for now.
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default 2
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 36
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config RGF_NUM_BANKS
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default 1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 30000000
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config HARVARD
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def_bool n
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config FLASH_BASE_ADDRESS
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default 0x00000000
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config FLASH_SIZE
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default 0
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# em7d has no FLASH so size is 0.
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config SRAM_BASE_ADDRESS
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default 0x10000000
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config SRAM_SIZE
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default 131072
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config ICCM_BASE_ADDRESS
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default 0x00000000
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config ICCM_SIZE
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default 256
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config DCCM_BASE_ADDRESS
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default 0x80000000
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config DCCM_SIZE
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default 128
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config CACHE_FLUSHING
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def_bool y
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if GPIO
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config GPIO_DW
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def_bool y
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if GPIO_DW
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config GPIO_DW_0
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def_bool y
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if GPIO_DW_0
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config GPIO_DW_0_NAME
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default "GPIO_PORTA"
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config GPIO_DW_0_IRQ_PRI
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default 1
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endif # GPIO_DW_0
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config GPIO_DW_1
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def_bool y
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if GPIO_DW_1
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config GPIO_DW_1_NAME
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default "GPIO_PORTB"
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config GPIO_DW_1_IRQ_PRI
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default 1
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endif # GPIO_DW_1
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config GPIO_DW_2
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def_bool y
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if GPIO_DW_2
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config GPIO_DW_2_IRQ_PRI
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default 1
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config GPIO_DW_2_NAME
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default "GPIO_PORTC"
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endif # GPIO_DW_2
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config GPIO_DW_3
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def_bool y
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if GPIO_DW_3
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config GPIO_DW_3_IRQ_PRI
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default 1
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config GPIO_DW_3_NAME
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default "GPIO_PORTD"
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endif # GPIO_DW_3
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endif # GPIO_DW
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endif # GPIO
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if I2C
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config I2C_CLOCK_SPEED
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default 100
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config I2C_DW
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def_bool y
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if I2C_DW
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config I2C_0
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def_bool y
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if I2C_0
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config I2C_0_NAME
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default "I2C_0"
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config I2C_0_DEFAULT_CFG
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default 0x3
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config I2C_0_IRQ_PRI
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default 1
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endif # I2C_0
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config I2C_1
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def_bool y
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if I2C_1
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config I2C_1_NAME
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default "I2C_1"
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config I2C_1_DEFAULT_CFG
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default 0x3
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config I2C_1_IRQ_PRI
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default 1
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endif # I2C_1
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endif # I2C_DW
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endif # I2C
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if UART_NS16550
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config UART_NS16550_PORT_0
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def_bool n
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if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_NAME
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default "UART_0"
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config UART_NS16550_PORT_0_IRQ_PRI
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default 1
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config UART_NS16550_PORT_0_BAUD_RATE
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default 115200
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config UART_NS16550_PORT_0_OPTIONS
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default 0
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endif # UART_NS16550_PORT_0
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config UART_NS16550_PORT_1
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def_bool y
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if UART_NS16550_PORT_1
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config UART_NS16550_PORT_1_NAME
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default "UART_1"
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config UART_NS16550_PORT_1_IRQ_PRI
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default 1
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config UART_NS16550_PORT_1_BAUD_RATE
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default 115200
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config UART_NS16550_PORT_1_OPTIONS
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default 0
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endif # UART_NS16550_PORT_1
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endif # UART_NS16550
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if UART_CONSOLE
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config UART_CONSOLE_ON_DEV_NAME
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default "UART_1"
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endif
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if SPI
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config SPI_DW
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def_bool y
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if SPI_DW
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config SPI_DW_CLOCK_GATE
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def_bool n
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config SPI_DW_FIFO_DEPTH
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default 32
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config SPI_DW_ARC_AUX_REGS
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def_bool n
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config SPI_0
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def_bool y
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if SPI_0
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config SPI_0_IRQ_PRI
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default 0
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endif # SPI_0
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config SPI_1
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def_bool y
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if SPI_1
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config SPI_1_IRQ_PRI
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default 0
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endif # SPI_1
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endif # SPI_DW
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endif # SPI
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endif #SOC_EM7D
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