329 lines
7.8 KiB
C
329 lines
7.8 KiB
C
/*
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* Copyright (c) 2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT altr_pio_1_0
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#define ALTERA_AVALON_PIO_DATA_OFFSET 0x00
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#define ALTERA_AVALON_PIO_DIRECTION_OFFSET 0x04
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#define ALTERA_AVALON_PIO_IRQ_OFFSET 0x08
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#define ALTERA_AVALON_PIO_SET_BITS 0x10
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#define ALTERA_AVALON_PIO_CLEAR_BITS 0x14
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typedef void (*altera_cfg_func_t)(void);
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struct gpio_altera_config {
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struct gpio_driver_config common;
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uintptr_t reg_base;
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uint32_t irq_num;
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uint8_t direction;
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uint8_t outset;
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uint8_t outclear;
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altera_cfg_func_t cfg_func;
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};
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struct gpio_altera_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* list of callbacks */
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sys_slist_t cb;
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struct k_spinlock lock;
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};
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static bool gpio_pin_direction(const struct device *dev, uint32_t pin_mask)
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{
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const struct gpio_altera_config *cfg = dev->config;
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const int direction = cfg->direction;
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uintptr_t reg_base = cfg->reg_base;
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uint32_t addr;
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uint32_t pin_direction;
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if (pin_mask == 0) {
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return -EINVAL;
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}
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/* Check if the direction is Bidirectional */
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if (direction != 0) {
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return -EINVAL;
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}
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addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET;
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pin_direction = sys_read32(addr);
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if (!(pin_direction & pin_mask)) {
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return false;
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}
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return true;
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}
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static int gpio_altera_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_altera_config *cfg = dev->config;
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struct gpio_altera_data * const data = dev->data;
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const int port_pin_mask = cfg->common.port_pin_mask;
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const int direction = cfg->direction;
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uintptr_t reg_base = cfg->reg_base;
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k_spinlock_key_t key;
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uint32_t addr;
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/* Check if pin number is within range */
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if ((port_pin_mask & BIT(pin)) == 0) {
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return -EINVAL;
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}
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/* Check if the direction is Bidirectional */
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if (direction != 0) {
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return -EINVAL;
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}
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addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET;
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key = k_spin_lock(&data->lock);
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if (flags == GPIO_INPUT) {
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sys_clear_bits(addr, BIT(pin));
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} else if (flags == GPIO_OUTPUT) {
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sys_set_bits(addr, BIT(pin));
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} else {
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return -EINVAL;
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_altera_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_altera_config *cfg = dev->config;
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uintptr_t reg_base = cfg->reg_base;
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uint32_t addr;
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addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
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if (value == NULL) {
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return -EINVAL;
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}
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*value = sys_read32((addr));
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return 0;
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}
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static int gpio_altera_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
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{
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const struct gpio_altera_config *cfg = dev->config;
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struct gpio_altera_data * const data = dev->data;
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const uint8_t outset = cfg->outset;
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const int port_pin_mask = cfg->common.port_pin_mask;
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uintptr_t reg_base = cfg->reg_base;
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uint32_t addr;
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k_spinlock_key_t key;
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if ((port_pin_mask & mask) == 0) {
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return -EINVAL;
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}
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if (!gpio_pin_direction(dev, mask)) {
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return -EINVAL;
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}
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key = k_spin_lock(&data->lock);
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if (outset) {
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addr = reg_base + ALTERA_AVALON_PIO_SET_BITS;
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sys_write32(mask, addr);
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} else {
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addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
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sys_set_bits(addr, mask);
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_altera_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
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{
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const struct gpio_altera_config *cfg = dev->config;
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struct gpio_altera_data * const data = dev->data;
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const uint8_t outclear = cfg->outclear;
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const int port_pin_mask = cfg->common.port_pin_mask;
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uintptr_t reg_base = cfg->reg_base;
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uint32_t addr;
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k_spinlock_key_t key;
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/* Check if mask range within 32 */
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if ((port_pin_mask & mask) == 0) {
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return -EINVAL;
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}
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if (!gpio_pin_direction(dev, mask)) {
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return -EINVAL;
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}
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key = k_spin_lock(&data->lock);
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if (outclear) {
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addr = reg_base + ALTERA_AVALON_PIO_CLEAR_BITS;
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sys_write32(mask, addr);
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} else {
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addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
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sys_clear_bits(addr, mask);
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_init(const struct device *dev)
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{
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const struct gpio_altera_config *cfg = dev->config;
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/* Configure GPIO device */
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cfg->cfg_func();
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return 0;
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}
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static int gpio_altera_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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ARG_UNUSED(trig);
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const struct gpio_altera_config *cfg = dev->config;
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struct gpio_altera_data * const data = dev->data;
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uintptr_t reg_base = cfg->reg_base;
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const int port_pin_mask = cfg->common.port_pin_mask;
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uint32_t addr;
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k_spinlock_key_t key;
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/* Check if pin number is within range */
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if ((port_pin_mask & BIT(pin)) == 0) {
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return -EINVAL;
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}
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if (!gpio_pin_direction(dev, BIT(pin))) {
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return -EINVAL;
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}
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addr = reg_base + ALTERA_AVALON_PIO_IRQ_OFFSET;
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key = k_spin_lock(&data->lock);
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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/* Disable interrupt of pin */
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sys_clear_bits(addr, BIT(pin));
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irq_disable(cfg->irq_num);
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break;
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case GPIO_INT_MODE_LEVEL:
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case GPIO_INT_MODE_EDGE:
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/* Enable interrupt of pin */
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sys_set_bits(addr, BIT(pin));
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irq_enable(cfg->irq_num);
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break;
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default:
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return -EINVAL;
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int gpio_altera_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_altera_data * const data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static void gpio_altera_irq_handler(const struct device *dev)
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{
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const struct gpio_altera_config *cfg = dev->config;
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struct gpio_altera_data *data = dev->data;
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uintptr_t reg_base = cfg->reg_base;
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uint32_t port_value;
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uint32_t addr;
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k_spinlock_key_t key;
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addr = reg_base + ALTERA_AVALON_PIO_IRQ_OFFSET;
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key = k_spin_lock(&data->lock);
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port_value = sys_read32(addr);
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sys_clear_bits(addr, port_value);
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k_spin_unlock(&data->lock, key);
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/* Call the corresponding callback registered for the pin */
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gpio_fire_callbacks(&data->cb, dev, port_value);
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}
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static const struct gpio_driver_api gpio_altera_driver_api = {
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.pin_configure = gpio_altera_configure,
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.port_get_raw = gpio_altera_port_get_raw,
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.port_set_masked_raw = NULL,
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.port_set_bits_raw = gpio_altera_port_set_bits_raw,
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.port_clear_bits_raw = gpio_altera_port_clear_bits_raw,
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.port_toggle_bits = NULL,
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.pin_interrupt_configure = gpio_altera_pin_interrupt_configure,
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.manage_callback = gpio_altera_manage_callback
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};
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#define GPIO_CFG_IRQ(idx, n) \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \
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COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, priority), \
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DT_INST_IRQ(n, priority), (0)), gpio_altera_irq_handler, \
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DEVICE_DT_INST_GET(n), 0); \
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#define CREATE_GPIO_DEVICE(n) \
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static void gpio_altera_cfg_func_##n(void); \
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static struct gpio_altera_data gpio_altera_data_##n; \
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static struct gpio_altera_config gpio_config_##n = { \
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.common = { \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.reg_base = DT_INST_REG_ADDR(n), \
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.direction = DT_INST_ENUM_IDX(n, direction), \
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.irq_num = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), (DT_INST_IRQN(n)), (0)),\
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.cfg_func = gpio_altera_cfg_func_##n, \
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.outset = DT_INST_PROP(n, outset), \
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.outclear = DT_INST_PROP(n, outclear), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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gpio_init, \
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NULL, \
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&gpio_altera_data_##n, \
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&gpio_config_##n, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_altera_driver_api); \
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\
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static void gpio_altera_cfg_func_##n(void) \
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{ \
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), GPIO_CFG_IRQ, (), n)\
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}
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DT_INST_FOREACH_STATUS_OKAY(CREATE_GPIO_DEVICE)
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