235 lines
6.7 KiB
Plaintext
235 lines
6.7 KiB
Plaintext
/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* NPCX9 series pinmux mapping table */
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#include "npcx/npcx9/npcx9-alts-map.dtsi"
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/* NPCX9 series mapping table between MIWU wui bits and source device */
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#include "npcx/npcx9/npcx9-miwus-wui-map.dtsi"
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/* NPCX9 series mapping table between MIWU groups and interrupts */
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#include "npcx/npcx9/npcx9-miwus-int-map.dtsi"
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/* NPCX9 series eSPI VW mapping table */
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#include "npcx/npcx9/npcx9-espi-vws-map.dtsi"
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/* NPCX9 series low-voltage io controls mapping table */
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#include "npcx/npcx9/npcx9-lvol-ctrl-map.dtsi"
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/* NPCX9 series power-switch-logic (PSL) io controls mapping table */
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#include "npcx/npcx9/npcx9-psl-ctrl-map.dtsi"
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/* Device tree declarations of npcx soc family */
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#include "npcx.dtsi"
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/ {
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def-io-conf-list {
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pinctrl-0 = <&alt0_gpio_no_spip
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&alt0_gpio_no_fpip
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&alt1_no_pwrgd
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&alta_no_peci_en
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&altd_npsl_in1_sl
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&altd_npsl_in2_sl
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&altd_psl_in3_sl
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&altd_psl_in4_sl
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&alt7_no_ksi0_sl
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&alt7_no_ksi1_sl
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&alt7_no_ksi2_sl
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&alt7_no_ksi3_sl
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&alt7_no_ksi4_sl
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&alt7_no_ksi5_sl
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&alt7_no_ksi6_sl
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&alt7_no_ksi7_sl
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&alt8_no_kso00_sl
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&alt8_no_kso01_sl
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&alt8_no_kso02_sl
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&alt8_no_kso03_sl
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&alt8_no_kso04_sl
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&alt8_no_kso05_sl
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&alt8_no_kso06_sl
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&alt8_no_kso07_sl
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&alt9_no_kso08_sl
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&alt9_no_kso09_sl
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&alt9_no_kso10_sl
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&alt9_no_kso11_sl
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&alt9_no_kso12_sl
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&alt9_no_kso13_sl
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&alt9_no_kso14_sl
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&alt9_no_kso15_sl
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&alta_no_kso16_sl
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&alta_no_kso17_sl
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&altg_psl_gpo_sl>;
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};
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soc {
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/* Specific soc devices in npcx9 series */
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itims: timer@400b0000 {
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compatible = "nuvoton,npcx-itim-timer";
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reg = <0x400b0000 0x2000
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0x400be000 0x2000>;
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reg-names = "evt_itim", "sys_itim";
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clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
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&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
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interrupts = <28 1>; /* Event timer interrupt */
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label = "ITIM";
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};
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uart1: serial@400e0000 {
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compatible = "nuvoton,npcx-uart";
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reg = <0x400E0000 0x2000>;
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interrupts = <33 3>;
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clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
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pinctrl-0 = <&altj_cr_sin1_sl1 &altj_cr_sout1_sl1>; /* PIN10.11 */
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uart-rx = <&wui_cr_sin1>;
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status = "disabled";
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label = "UART_1";
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};
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uart2: serial@400e2000 {
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compatible = "nuvoton,npcx-uart";
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reg = <0x400E2000 0x2000>;
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interrupts = <32 3>;
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clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
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pinctrl-0 = <&altj_cr_sin2_sl &altj_cr_sout2_sl>; /* PIN75.86 */
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uart-rx = <&wui_cr_sin2>;
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status = "disabled";
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label = "UART_2";
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};
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uart3: serial@400e4000 {
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compatible = "nuvoton,npcx-uart";
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reg = <0x400E4000 0x2000>;
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interrupts = <38 3>;
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clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
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pinctrl-0 = <&altj_cr_sin3_sl &altj_cr_sout3_sl>; /* PIND3.D6 */
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uart-rx = <&wui_cr_sin3>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: serial@400e6000 {
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compatible = "nuvoton,npcx-uart";
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reg = <0x400E6000 0x2000>;
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interrupts = <39 3>;
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clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
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pinctrl-0 = <&alte_cr_sin4_sl &alte_cr_sout4_sl>; /* PIN17.35 */
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uart-rx = <&wui_cr_sin4>;
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status = "disabled";
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label = "UART_4";
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};
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/* Default clock and power settings in npcx9 series */
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pcc: clock-controller@4000d000 {
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clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
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core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
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apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
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apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
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ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
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};
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/* Wake-up input source mapping for GPIOs in npcx9 series */
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gpio0: gpio@40081000 {
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wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
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&wui_io04 &wui_io05 &wui_io06 &wui_io07>;
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};
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gpio1: gpio@40083000 {
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wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
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&wui_io14 &wui_io15 &wui_io16 &wui_io17>;
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};
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gpio2: gpio@40085000 {
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wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
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&wui_io24 &wui_io25 &wui_io26 &wui_io27>;
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};
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gpio3: gpio@40087000 {
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wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
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&wui_io34 &wui_none &wui_io36 &wui_io37>;
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};
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gpio4: gpio@40089000 {
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wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
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&wui_io44 &wui_io45 &wui_io46 &wui_io47>;
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};
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gpio5: gpio@4008b000 {
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wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
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&wui_io54 &wui_io55 &wui_io56 &wui_io57>;
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};
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gpio6: gpio@4008d000 {
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wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
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&wui_io64 &wui_none &wui_io66 &wui_io67>;
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};
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gpio7: gpio@4008f000 {
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wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
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&wui_io74 &wui_io75 &wui_io76 &wui_none>;
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};
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gpio8: gpio@40091000 {
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wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
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&wui_none &wui_none &wui_none &wui_io87>;
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};
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gpio9: gpio@40093000 {
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wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
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&wui_io94 &wui_io95 &wui_io96 &wui_io97>;
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};
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gpioa: gpio@40095000 {
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wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
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&wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
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};
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gpiob: gpio@40097000 {
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wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
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&wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>;
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};
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gpioc: gpio@40099000 {
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wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
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&wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
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};
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gpiod: gpio@4009b000 {
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wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
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&wui_iod4 &wui_iod5 &wui_none &wui_none>;
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};
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gpioe: gpio@4009d000 {
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wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
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&wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
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};
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gpiof: gpio@4009f000 {
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wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
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&wui_iof4 &wui_iof5 &wui_none &wui_none>;
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};
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/* Supported channels for ADC0 in npcx9 series */
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adc0: adc@400d1000 {
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pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */
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&alt6_adc1_sl /* ADC1 - PIN44 */
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&alt6_adc2_sl /* ADC2 - PIN43 */
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&alt6_adc3_sl /* ADC3 - PIN42 */
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&alt6_adc4_sl /* ADC4 - PIN41 */
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&altf_adc5_sl /* ADC5 - PIN37 */
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&altf_adc6_sl /* ADC6 - PIN34 */
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&altf_adc7_sl /* ADC7 - PINE1 */
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&altf_adc8_sl /* ADC8 - PINF1 */
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&altf_adc9_sl /* ADC9 - PINF0 */
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&altf_adc10_sl /* ADC10 - PINE0 */
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&altf_adc11_sl>; /* ADC11 - PINC7 */
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threshold-reg-offset = <0x60>;
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threshold-count = <6>;
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};
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};
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soc-id {
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chip-id = <0x09>;
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revision-reg = <0x0000FFFC 4>;
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};
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};
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