Gerard Marull-Paretas f885763b50 arch: riscv: drop RISCV_HAS_CPU_IDLE ... Because it was exclusively used by the "common" RISC-V privileged code to build CPU idle routines that are now handled by arch level code. Also, all platforms defaulted to "y", making it pointless in practice. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2024-01-12 09:58:31 +01:00
..
andes_v5	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
common	soc: riscv: riscv-privileged: remove redundant idle implementation	2024-01-12 09:58:31 +01:00
efinix_sapphire	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
espressif_esp32	soc: riscv: espressif_esp32: use arch idle	2024-01-12 09:58:31 +01:00
gd_gd32	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
intel_niosv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
ite_ec	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
litex_vexriscv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
microchip_miv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
neorv32	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
openisa_rv32m1	…
opentitan	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
renode_virt	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
sifive_freedom	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
starfive_jh71xx	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
telink_tlsr	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
virt	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
CMakeLists.txt	soc: riscv: move privileged code to common folder	2024-01-09 09:40:07 +01:00