115 lines
2.7 KiB
C
115 lines
2.7 KiB
C
/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for the Quark SE BSP
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*
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* This module provides routines to initialize and support board-level
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* hardware for the Quark SE BSP.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <misc/printk.h>
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#include <misc/__assert.h>
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#include "soc.h"
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#include <uart.h>
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#include <init.h>
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#include "shared_mem.h"
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#include <mmustructs.h>
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#ifdef CONFIG_X86_MMU
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/* loapic */
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MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE);
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/*ioapic */
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MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE);
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/* peripherals */
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MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE);
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/* SCSS system control subsystem */
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MMU_BOOT_REGION(0xB0800000, 16*1024, MMU_ENTRY_WRITE);
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/* DMA */
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MMU_BOOT_REGION(0xB0700000, 4*1024, MMU_ENTRY_WRITE);
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/* USB */
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MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE);
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#endif /* CONFIG_X86_MMU */
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#ifdef CONFIG_ARC_INIT
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#define SCSS_REG_VAL(offset) \
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(*((volatile u32_t *)(SCSS_REGISTER_BASE+offset)))
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_ARC_INIT_LEVEL
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#include <logging/sys_log.h>
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/**
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*
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* @brief ARC Init
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*
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* This routine initialize the ARC reset vector and
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* starts the ARC processor.
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* @return N/A
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*/
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/* This function is also called at deep sleep resume. */
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int _arc_init(struct device *arg)
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{
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u32_t *reset_vector;
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ARG_UNUSED(arg);
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if (!SCSS_REG_VAL(SCSS_SS_STS)) {
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/* ARC shouldn't already be running! */
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printk("ARC core already running!");
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return -EIO;
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}
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/* Address of ARC side __reset stored in the first 4 bytes of arc.bin,
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* we read the value and stick it in shared_mem->arc_start which is
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* the beginning of the address space at 0xA8000000 */
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reset_vector = (u32_t *)RESET_VECTOR;
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SYS_LOG_DBG("Reset vector address: %x", *reset_vector);
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shared_data->arc_start = *reset_vector;
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shared_data->flags = 0;
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if (!shared_data->arc_start) {
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/* Reset vector points to NULL => skip ARC init. */
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SYS_LOG_DBG("Reset vector is NULL, skipping ARC init.");
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goto skip_arc_init;
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}
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#ifndef CONFIG_ARC_GDB_ENABLE
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/* Start the CPU */
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SCSS_REG_VAL(SCSS_SS_CFG) |= ARC_RUN_REQ_A;
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#endif
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SYS_LOG_DBG("Waiting for arc to start...");
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/* Block until the ARC core actually starts up */
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while (SCSS_REG_VAL(SCSS_SS_STS) & 0x4000) {
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}
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/* Block until ARC's quark_se_init() sets a flag indicating it is ready,
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* if we get stuck here ARC has run but has exploded very early */
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SYS_LOG_DBG("Waiting for arc to init...");
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while (!(shared_data->flags & ARC_READY)) {
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}
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skip_arc_init:
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return 0;
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}
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SYS_INIT(_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /*CONFIG_ARC_INIT*/
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