113 lines
2.0 KiB
Plaintext
113 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_lpc54xxx_m4.dtsi>
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#include "lpcxpresso54114.dtsi"
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "NXP LPCXpresso54114 board";
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compatible = "nxp,lpc54xxx", "nxp,lpc";
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aliases{
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sw0 = &user_button_1;
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sw1 = &user_button_2;
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sw2 = &user_button_3;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &flexcomm0;
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zephyr,shell-uart = &flexcomm0;
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zephyr,code-partition = &slot0_partition;
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_1: button_0 {
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label = "User SW1";
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gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_2: button_1 {
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label = "User SW2";
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gpios = <&gpio0 31 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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zephyr,code = <INPUT_KEY_1>;
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};
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user_button_3: button_2 {
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label = "User SW3";
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gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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zephyr,code = <INPUT_KEY_2>;
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};
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};
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};
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/*
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* Default for this board is to allocate SRAM0-1 to M4 CPU but the
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* application can have an application specific device tree to
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* allocate the SRAM0-3 differently.
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*
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*/
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&sram0 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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&cpu0 {
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clock-frequency = <48000000>;
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};
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&mailbox0 {
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status = "okay";
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};
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&red_led {
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status = "okay";
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};
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&green_led {
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status = "okay";
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};
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&blue_led {
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status = "okay";
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};
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&flexcomm0 {
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status = "okay";
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};
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&flexcomm4 {
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status = "okay";
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};
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&flexcomm5 {
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status = "okay";
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};
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&flash0 {
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/*
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* LPC flash controller requires minimum 256 byte write to flash,
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* so MCUBoot is not supported. Just provide storage and code partition.
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*/
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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slot0_partition: partition@0 {
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label = "image-0";
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reg = <0x00000000 DT_SIZE_K(196)>;
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};
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storage_partition: partition@30000 {
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label = "storage";
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reg = <0x00030000 DT_SIZE_K(64)>;
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};
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};
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};
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