131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_pinctrl
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#include <drivers/pinmux.h>
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#include <kernel.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pimux_npcx, LOG_LEVEL_ERR);
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/* Driver config */
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struct npcx_pinctrl_config {
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/* scfg device base address */
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uintptr_t base_scfg;
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uintptr_t base_glue;
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};
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/*
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* Get io list which default functionality are not IOs. Then switch them to
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* GPIO in pin-mux init function.
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*
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* def_io_conf: def_io_conf_list {
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* compatible = "nuvoton,npcx-pinctrl-def";
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* pinctrl-0 = <&alt0_gpio_no_spip
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* &alt0_gpio_no_fpip
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* ...>;
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* };
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*/
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static const struct npcx_alt def_alts[] =
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NPCX_DT_IO_ALT_ITEMS_LIST(nuvoton_npcx_pinctrl_def, 0);
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static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
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static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
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.base_scfg = DT_INST_REG_ADDR_BY_NAME(0, scfg),
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.base_glue = DT_INST_REG_ADDR_BY_NAME(0, glue),
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};
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/* Driver convenience defines */
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#define HAL_SFCG_INST() (struct scfg_reg *)(npcx_pinctrl_cfg.base_scfg)
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#define HAL_GLUE_INST() (struct glue_reg *)(npcx_pinctrl_cfg.base_glue)
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/* Pin-control local functions */
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static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
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{
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const uint32_t scfg_base = npcx_pinctrl_cfg.base_scfg;
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uint8_t alt_mask = BIT(alt->bit);
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/*
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* alt_fun == 0 means select GPIO, otherwise Alternate Func.
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* inverted == 0:
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* Set devalt bit to select Alternate Func.
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* inverted == 1:
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* Clear devalt bit to select Alternate Func.
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*/
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if (!!alt_func != !!alt->inverted) {
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NPCX_DEVALT(scfg_base, alt->group) |= alt_mask;
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} else {
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NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;
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}
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}
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/* Platform specific pin-control functions */
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void npcx_pinctrl_mux_configure(const struct npcx_alt *alts_list,
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uint8_t alts_size, int altfunc)
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{
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int i;
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for (i = 0; i < alts_size; i++, alts_list++) {
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npcx_pinctrl_alt_sel(alts_list, altfunc);
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}
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}
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void npcx_lvol_pads_configure(void)
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{
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const uint32_t scfg_base = npcx_pinctrl_cfg.base_scfg;
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for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
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NPCX_LV_GPIO_CTL(scfg_base, def_lvols[i].ctrl)
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|= BIT(def_lvols[i].bit);
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LOG_DBG("IO%x%x turn on low-voltage", def_lvols[i].io_port,
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def_lvols[i].io_bit);
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}
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}
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void npcx_pinctrl_i2c_port_sel(int controller, int port)
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{
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struct glue_reg *const inst_glue = HAL_GLUE_INST();
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if (port != 0) {
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inst_glue->SMB_SEL |= BIT(controller);
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} else {
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inst_glue->SMB_SEL &= ~BIT(controller);
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}
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}
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/* Pin-control driver registration */
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static int npcx_pinctrl_init(const struct device *dev)
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{
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struct scfg_reg *inst_scfg = HAL_SFCG_INST();
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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/*
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* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
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* for more information. It will be fixed in next chip.
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*/
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inst_scfg->DEVCNT |= BIT(7);
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#endif
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/* Change all pads whose default functionality isn't IO to GPIO */
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npcx_pinctrl_mux_configure(def_alts, ARRAY_SIZE(def_alts), 0);
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/* Configure default low-voltage pads */
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npcx_lvol_pads_configure();
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return 0;
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}
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DEVICE_DT_DEFINE(DT_NODELABEL(scfg),
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&npcx_pinctrl_init,
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device_pm_control_nop,
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NULL, &npcx_pinctrl_cfg,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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NULL);
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