107 lines
2.0 KiB
Plaintext
107 lines
2.0 KiB
Plaintext
# Copyright 2019,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_LPC55XXX
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config NUM_IRQS
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# must be >= the highest interrupt number used
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default 60
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 144000000 if INIT_PLL1
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default 96000000
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# Indicates the second core will be enabled, and the part will run
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# in dual core mode.
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config SECOND_CORE_MCUX
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depends on HAS_MCUX
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
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# Move the LMA for the second core image to be in the flash region of primary
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# core, so that JLink flash will load it correctly.
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config BUILD_OUTPUT_ADJUST_LMA
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depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
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default "0x10000000"
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# SRAM controllers 1,2,3, and 4 are disabled at reset.
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# By default, CMSIS SystemInit will enable the clock to these RAM banks.
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# Disable this Kconfig to leave the ram banks untouched out of reset.
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config LPC55XXX_SRAM_CLOCKS
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default y
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# Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
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# By default, USB RAM is assumed to be present.
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# Disable this Kconfig in case there is no dedicated USB RAM.
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config LPC55XXX_USB_RAM
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default y
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if SOC_LPC55S06
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config LPC55XXX_USB_RAM
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default n
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endif # SOC_LPC55S06
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if SOC_LPC55S16
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config CAN_MCUX_MCAN
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default y
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depends on CAN
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choice USB_MCUX_CONTROLLER_TYPE
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default USB_DC_NXP_LPCIP3511
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endchoice
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endif # SOC_LPC55S16
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if SOC_LPC55S28
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choice USB_MCUX_CONTROLLER_TYPE
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default USB_DC_NXP_LPCIP3511
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endchoice
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endif # SOC_LPC55S28
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if SOC_LPC55S36
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choice USB_MCUX_CONTROLLER_TYPE
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default USB_DC_NXP_LPCIP3511
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endchoice
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config LPC55XXX_USB_RAM
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default n
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endif # SOC_LPC55S36
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if SOC_LPC55S69
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config SOC_FLASH_MCUX
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default y
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depends on FLASH
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depends on !TRUSTED_EXECUTION_NONSECURE
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choice USB_MCUX_CONTROLLER_TYPE
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default USB_DC_NXP_LPCIP3511
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endchoice
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config I2S_MCUX_FLEXCOMM
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select INIT_PLL0
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endif # SOC_LPC55S69
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if SOC_LPC55S69_CPU1
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config GPIO
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default y
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config SERIAL
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default n
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endif # SOC_LPC55S69_CPU1
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endif # SOC_SERIES_LPC55XXX
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