100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <zephyr/arch/cpu.h>
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#define LPSCI0SRC_MCGFLLCLK (1)
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#define CLOCK_NODEID(clk) \
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DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
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#define CLOCK_DIVIDER(clk) \
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DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static ALWAYS_INLINE void clock_init(void)
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{
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/*
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* Core clock: 48MHz
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* Bus clock: 24MHz
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*/
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const mcg_pll_config_t pll0Config = {
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.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
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};
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const sim_clock_config_t simConfig = {
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.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
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.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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};
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const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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} };
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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/* Passing the XTAL0 frequency to clock driver. */
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
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CLOCK_SetSimConfig(&simConfig);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
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CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
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#endif
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#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency));
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#endif
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}
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static int kl2x_init(void)
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{
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/* Initialize system clock to 48 MHz */
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clock_init();
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return 0;
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}
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#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
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void z_arm_platform_init(void)
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{
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SystemInit();
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}
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#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
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SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
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