Daniel Maslowski 6b495ceda9 dts: jh7110: fix memory definitions ... The L2LIM is 2MB in size, see: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/u74_memory_map.html Rename it since there are other memory blocks such as the DTIM for the S7. Signed-off-by: Daniel Maslowski <info@orangecms.org>		2024-04-09 14:20:39 +02:00
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andes	dts/riscv/andes: add `andestech,andescore-v5` compatible string	2024-01-31 10:41:49 +01:00
efinix	dts/riscv/efinix: add the `efinix,vexriscv-sapphire` compatible string	2024-01-31 10:41:49 +01:00
espressif/esp32c3	dts: bindings: can: remove optional sample point properties	2024-03-17 15:36:19 +01:00
gd	…
ite	it82xx2: Add missing ISRs for gpioj	2024-02-27 14:44:41 +01:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	…
nordic	dts: Remove support for nRF54H20 EngA	2024-03-18 19:11:36 +00:00
openisa	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
sifive	…
starfive	dts: jh7110: fix memory definitions	2024-04-09 14:20:39 +02:00
telink	…
neorv32.dtsi	…
renode_riscv32_virt.dtsi	…
riscv32-litex-vexriscv.dtsi	dts/riscv/litex: add `litex,vexriscv-standard` compatible string	2024-01-31 10:41:49 +01:00
virt.dtsi	…