36 lines
1002 B
ArmAsm
36 lines
1002 B
ArmAsm
/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc.h"
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#include "soc/interrupt_reg.h"
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#include "riscv/rvruntime-frames.h"
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#include "soc/soc_caps.h"
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#include <zephyr/toolchain.h>
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/* Imports */
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GTEXT(_isr_wrapper)
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.global _esp32c3_vector_table
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.section .exception_vectors.text
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.balign 0x100
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.type _esp32c3_vector_table, @function
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_esp32c3_vector_table:
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.option push
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.option norvc
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.rept (32)
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j _isr_wrapper /* 32 identical entries, all pointing to the interrupt handler */
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.endr
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