119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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*
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* @brief This file has the WinBond SPI flash private definitions
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*/
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#ifndef ZEPHYR_DRIVERS_FLASH_SPI_FLASH_W25QXXDV_DEFS_H_
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#define ZEPHYR_DRIVERS_FLASH_SPI_FLASH_W25QXXDV_DEFS_H_
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/* Status Registers
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* S7 S6 S5 S4 S3 S2 S1 S0
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* +-------------------------------------------------------+
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* | SRP0 | SEC | TB | BP2 | BP1 | BP0 | WEL | BUSY |
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* +-------------------------------------------------------+
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*
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* BUSY - Erase/Write In Progress - 1 device is executing a command, 0 ready for command
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* WEL - Write Enable Latch - 1 write enable is received, 0 completeion of
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* a Write Disable, Page Program, Erase, Write Status Register
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*
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* S15 S14 S13 S12 S11 S10 S9 S8
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* +-------------------------------------------------------+
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* | SUS | CMP | LB3 | LB2 | LB1 | xxx | QE | SRP1 |
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* +-------------------------------------------------------+
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*
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* S23 S22 S21 S20 S19 S18 S17 S16
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* +----------------------------------------------------------+
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* | HOLD/RST | DRV1 | DRV0 | xxx | xxx | WPS | xxx | xxx |
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* +----------------------------------------------------------+
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*/
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#define W25QXXDV_RDID_VALUE (0x00ef4015)
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#define W25QXXDV_MAX_LEN_REG_CMD (6)
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#define W25QXXDV_OPCODE_LEN (1)
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#define W25QXXDV_ADDRESS_WIDTH (3)
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#define W25QXXDV_LEN_CMD_ADDRESS (4)
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#define W25QXXDV_LEN_CMD_AND_ID (4)
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/* relevant status register bits */
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#define W25QXXDV_WIP_BIT (0x1 << 0)
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#define W25QXXDV_WEL_BIT (0x1 << 1)
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#define W25QXXDV_SRWD_BIT (0x1 << 7)
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#define W25QXXDV_TB_BIT (0x1 << 3)
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#define W25QXXDV_SR_BP_OFFSET (2)
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/* relevant security register bits */
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#define W25QXXDV_SECR_WPSEL_BIT (0x1 << 7)
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#define W25QXXDV_SECR_EFAIL_BIT (0x1 << 6)
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#define W25QXXDV_SECR_PFAIL_BIT (0x1 << 5)
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/* supported erase size */
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#define W25QXXDV_SECTOR_SIZE (0x1000)
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#define W25QXXDV_BLOCK32K_SIZE (0x8000)
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#define W25QXXDV_BLOCK_SIZE (0x10000)
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#define W25QXXDV_SECTOR_MASK (0xFFF)
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/* ID commands */
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#define W25QXXDV_CMD_RDID 0x9F
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#define W25QXXDV_CMD_RES 0xAB
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#define W25QXXDV_CMD_REMS 0x90
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#define W25QXXDV_CMD_QPIID 0xAF
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#define W25QXXDV_CMD_UNID 0x4B
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/*Register commands */
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#define W25QXXDV_CMD_WRSR 0x01
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#define W25QXXDV_CMD_RDSR 0x05
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#define W25QXXDV_CMD_RDSR2 0x35
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#define W25QXXDV_CMD_WRSCUR 0x2F
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#define W25QXXDV_CMD_RDSCUR 0x48
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/* READ commands */
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#define W25QXXDV_CMD_READ 0x03
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#define W25QXXDV_CMD_2READ 0xBB
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#define W25QXXDV_CMD_4READ 0xEB
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#define W25QXXDV_CMD_FASTREAD 0x0B
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#define W25QXXDV_CMD_DREAD 0x3B
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#define W25QXXDV_CMD_QREAD 0x6B
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#define W25QXXDV_CMD_RDSFDP 0x5A
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/* Program commands */
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#define W25QXXDV_CMD_WREN 0x06
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#define W25QXXDV_CMD_WRDI 0x04
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#define W25QXXDV_CMD_PP 0x02
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#define W25QXXDV_CMD_4PP 0x32
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#define W25QXXDV_CMD_WRENVSR 0x50
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/* Erase commands */
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#define W25QXXDV_CMD_SE 0x20
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#define W25QXXDV_CMD_BE32K 0x52
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#define W25QXXDV_CMD_BE 0xD8
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#define W25QXXDV_CMD_CE 0x60
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/* Mode setting commands */
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#define W25QXXDV_CMD_DP 0xB9
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#define W25QXXDV_CMD_RDP 0xAB
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/* Reset commands */
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#define W25QXXDV_CMD_RSTEN 0x66
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#define W25QXXDV_CMD_RST 0x99
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#define W25QXXDV_CMD_RSTQIO 0xF5
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/* Security commands */
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#define W25QXXDV_CMD_ERSR 0x44
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#define W25QXXDV_CMD_PRSR 0x42
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/* Suspend/Resume commands */
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#define W25QXXDV_CMD_PGM_ERS_S 0x75
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#define W25QXXDV_CMD_PGM_ERS_R 0x7A
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#define W25QXXDV_CMD_NOP 0x00
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#endif /*ZEPHYR_DRIVERS_FLASH_SPI_FLASH_W25QXXDV_DEFS_H_*/
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