317 lines
8.4 KiB
C
317 lines
8.4 KiB
C
/* pci_config.c - PCI bus support */
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/*
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* Copyright (c) 2009-2010, 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module implements the PCI config space access functions
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <pci/pci_mgr.h>
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#include <string.h>
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#ifdef __MSIX_DEBUG__
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#include <misc/printk.h>
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#define _DEBUG_PRINT(fmt, args...) printk(fmt, ##args)
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#else
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#define _DEBUG_PRINT(fmt, args...) \
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do { \
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} while (0)
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#endif
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/**
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*
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* @brief Write a 32bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number
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* @param func_no Function number
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* @return N/A
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*/
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void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint32_t data)
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{
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union pci_addr_reg pci_addr;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = 0;
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/* write to the PCI controller */
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
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}
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/**
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*
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* @brief Write a 16bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* @return N/A
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*/
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void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint16_t data)
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{
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union pci_addr_reg pci_addr;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = offset & 2;
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/* write to the PCI controller */
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint16_t), data);
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}
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/**
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*
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* @brief Write a 8bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* @return N/A
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*/
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void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint8_t data)
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{
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union pci_addr_reg pci_addr;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = offset % 4;
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/* write to the PCI controller */
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint8_t), data);
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}
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/**
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*
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* @brief Read a 32bit data from pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* @return N/A
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*
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*/
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void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint32_t *data)
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{
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union pci_addr_reg pci_addr;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = 0;
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/* read from the PCI controller */
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pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
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}
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/**
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*
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* @brief Read in a 16bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* @return N/A
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*
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*/
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void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint16_t *data)
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{
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union pci_addr_reg pci_addr;
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uint32_t pci_data;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = offset & 2;
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/* read from the PCI controller */
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pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint16_t), &pci_data);
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/* return the data */
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*data = (uint16_t)pci_data;
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}
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/**
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*
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* @brief Read in a 8bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* @return N/A
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*
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*/
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void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint8_t *data)
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{
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union pci_addr_reg pci_addr;
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uint32_t pci_data;
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/* create the PCI address we're going to access */
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pci_addr.field.bus = bus_no;
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pci_addr.field.device = device_no;
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pci_addr.field.func = func_no;
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pci_addr.field.reg = offset / 4;
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pci_addr.field.offset = offset % 4;
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/* read from the PCI controller */
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pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint8_t), &pci_data);
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/* return the data */
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*data = (uint8_t)pci_data;
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}
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/**
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*
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* @brief Find extended capability in ECP linked list
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*
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* This routine searches for an extended capability in the linked list of
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* capabilities in config space. If found, the offset of the first byte
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* of the capability of interest in config space is returned via pOffset.
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*
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* @param ext_cap_find_id Extended capabilities ID to search for.
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* @param bus PCI bus number.
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* @param device PCI device number.
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* @param function PCI function number.
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* @param p_offset Returned config space offset.
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*
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* @return 0 if Extended Capability found, -1 otherwise
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*
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*/
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int pci_config_ext_cap_ptr_find(uint8_t ext_cap_find_id, uint32_t bus,
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uint32_t device, uint32_t function,
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uint8_t *p_offset)
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{
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uint16_t tmp_stat;
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uint8_t tmp_offset;
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uint8_t cap_offset = 0x00;
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uint8_t cap_id = 0x00;
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/* Check to see if the device has any extended capabilities */
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pci_config_in_word(bus, device, function, PCI_CFG_STATUS, &tmp_stat);
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if ((tmp_stat & PCI_STATUS_NEW_CAP) == 0) {
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return -1;
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}
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/* Get the initial ECP offset and make longword aligned */
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pci_config_in_byte(bus, device, function, PCI_CFG_CAP_PTR, &cap_offset);
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cap_offset &= ~0x02;
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/* Bounds check the ECP offset */
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if (cap_offset < 0x40) {
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return -1;
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}
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/* Look for the specified Extended Cap item in the linked list */
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while (cap_offset != 0x00) {
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/* Get the Capability ID and check */
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pci_config_in_byte(bus, device, function, (int)cap_offset, &cap_id);
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if (cap_id == ext_cap_find_id) {
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*p_offset = cap_offset;
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return 0;
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}
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/* Get the offset to the next New Capabilities item */
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tmp_offset = cap_offset + (uint8_t)0x01;
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pci_config_in_byte(bus, device, function, (int)tmp_offset, &cap_offset);
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}
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return -1;
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}
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