175 lines
3.8 KiB
Plaintext
175 lines
3.8 KiB
Plaintext
/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l1/stm32l1-pinctrl.dtsi>
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m3";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v1";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v1";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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pinctrl: pin-controller@40020000 {
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compatible = "st,stm32-pinmux";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40020000 0x2000>;
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gpioa: gpio@40020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@40020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@40020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
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label = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@40021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
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label = "GPIOE";
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};
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gpioh: gpio@40021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
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label = "GPIOH";
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};
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};
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rcc: rcc@40023800 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x40023800 0x400>;
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label = "STM32_CLK_RCC";
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};
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flash-controller@40023c00 {
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compatible = "st,stm32l1-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40023c00 0x400>;
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interrupts = <4 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <4>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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