395 lines
9.4 KiB
C
395 lines
9.4 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <device.h>
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#include <spi.h>
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#include <gpio.h>
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#include <board.h>
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#include "qm_ss_spi.h"
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#include "qm_ss_isr.h"
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#include "ss_clk.h"
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struct ss_pending_transfer {
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struct device *dev;
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qm_ss_spi_async_transfer_t xfer;
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};
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static struct ss_pending_transfer pending_transfers[2];
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struct ss_spi_qmsi_config {
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qm_ss_spi_t spi;
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#ifdef CONFIG_SPI_CS_GPIO
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char *cs_port;
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uint32_t cs_pin;
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#endif
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};
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struct ss_spi_qmsi_runtime {
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#ifdef CONFIG_SPI_CS_GPIO
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struct device *gpio_cs;
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#endif
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device_sync_call_t sync;
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struct nano_sem sem;
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qm_ss_spi_config_t cfg;
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int rc;
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bool loopback;
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};
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static inline qm_ss_spi_bmode_t config_to_bmode(uint8_t mode)
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{
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switch (mode) {
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case SPI_MODE_CPHA:
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return QM_SS_SPI_BMODE_1;
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case SPI_MODE_CPOL:
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return QM_SS_SPI_BMODE_2;
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case SPI_MODE_CPOL | SPI_MODE_CPHA:
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return QM_SS_SPI_BMODE_3;
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default:
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return QM_SS_SPI_BMODE_0;
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}
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}
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#ifdef CONFIG_SPI_CS_GPIO
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static void spi_control_cs(struct device *dev, bool active)
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{
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struct ss_spi_qmsi_runtime *context = dev->driver_data;
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struct ss_spi_qmsi_config *config = dev->config->config_info;
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struct device *gpio = context->gpio_cs;
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if (!gpio)
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return;
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gpio_pin_write(gpio, config->cs_pin, !active);
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}
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#endif
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static int ss_spi_qmsi_configure(struct device *dev,
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struct spi_config *config)
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{
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struct ss_spi_qmsi_runtime *context = dev->driver_data;
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qm_ss_spi_config_t *cfg = &context->cfg;
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cfg->frame_size = SPI_WORD_SIZE_GET(config->config) - 1;
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cfg->bus_mode = config_to_bmode(SPI_MODE(config->config));
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/* As loopback is implemented inside the controller,
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* the bus mode doesn't matter.
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*/
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context->loopback = SPI_MODE(config->config) & SPI_MODE_LOOP;
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cfg->clk_divider = config->max_sys_freq;
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/* Will set the configuration before the transfer starts */
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return 0;
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}
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static void spi_qmsi_callback(void *data, int error, qm_ss_spi_status_t status,
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uint16_t len)
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{
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struct ss_spi_qmsi_config *spi_config =
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((struct device *)data)->config->config_info;
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qm_ss_spi_t spi_id = spi_config->spi;
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struct ss_pending_transfer *pending = &pending_transfers[spi_id];
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struct device *dev = pending->dev;
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struct ss_spi_qmsi_runtime *context;
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if (!dev)
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return;
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context = dev->driver_data;
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#ifdef CONFIG_SPI_CS_GPIO
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spi_control_cs(dev, false);
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#endif
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pending->dev = NULL;
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context->rc = error;
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device_sync_call_complete(&context->sync);
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}
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static int ss_spi_qmsi_slave_select(struct device *dev, uint32_t slave)
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{
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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qm_ss_spi_t spi_id = spi_config->spi;
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return qm_ss_spi_slave_select(spi_id, 1 << (slave - 1)) ? -EIO : 0;
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}
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static inline uint8_t frame_size_to_dfs(qm_ss_spi_frame_size_t frame_size)
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{
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if (frame_size <= QM_SS_SPI_FRAME_SIZE_8_BIT) {
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return 1;
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}
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if (frame_size <= QM_SS_SPI_FRAME_SIZE_16_BIT) {
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return 2;
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}
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/* This should never happen, it will crash later on. */
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return 0;
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}
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static int ss_spi_qmsi_transceive(struct device *dev,
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const void *tx_buf, uint32_t tx_buf_len,
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void *rx_buf, uint32_t rx_buf_len)
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{
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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qm_ss_spi_t spi_id = spi_config->spi;
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struct ss_spi_qmsi_runtime *context = dev->driver_data;
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qm_ss_spi_config_t *cfg = &context->cfg;
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uint8_t dfs = frame_size_to_dfs(cfg->frame_size);
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qm_ss_spi_async_transfer_t *xfer;
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int rc;
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nano_sem_take(&context->sem, TICKS_UNLIMITED);
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if (pending_transfers[spi_id].dev) {
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nano_sem_give(&context->sem);
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return -EBUSY;
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}
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pending_transfers[spi_id].dev = dev;
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nano_sem_give(&context->sem);
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xfer = &pending_transfers[spi_id].xfer;
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xfer->rx = rx_buf;
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xfer->rx_len = rx_buf_len / dfs;
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xfer->tx = (uint8_t *)tx_buf;
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xfer->tx_len = tx_buf_len / dfs;
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xfer->callback_data = dev;
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xfer->callback = spi_qmsi_callback;
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if (tx_buf_len == 0) {
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cfg->transfer_mode = QM_SS_SPI_TMOD_RX;
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} else if (rx_buf_len == 0) {
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cfg->transfer_mode = QM_SS_SPI_TMOD_TX;
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} else {
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cfg->transfer_mode = QM_SS_SPI_TMOD_TX_RX;
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}
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if (context->loopback) {
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uint32_t ctrl;
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if (spi_id == 0) {
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ctrl = __builtin_arc_lr(QM_SS_SPI_0_BASE +
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QM_SS_SPI_CTRL);
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ctrl |= BIT(11);
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__builtin_arc_sr(ctrl, QM_SS_SPI_0_BASE +
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QM_SS_SPI_CTRL);
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} else {
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ctrl = __builtin_arc_lr(QM_SS_SPI_1_BASE +
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QM_SS_SPI_CTRL);
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ctrl |= BIT(11);
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__builtin_arc_sr(ctrl, QM_SS_SPI_1_BASE +
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QM_SS_SPI_CTRL);
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}
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}
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rc = qm_ss_spi_set_config(spi_id, cfg);
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if (rc != 0) {
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return -EINVAL;
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}
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#ifdef CONFIG_SPI_CS_GPIO
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spi_control_cs(dev, true);
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#endif
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rc = qm_ss_spi_irq_transfer(spi_id, xfer);
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if (rc != 0) {
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#ifdef CONFIG_SPI_CS_GPIO
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spi_control_cs(dev, false);
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#endif
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return -EIO;
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}
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device_sync_call_wait(&context->sync);
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return context->rc ? -EIO : 0;
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}
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static struct spi_driver_api ss_spi_qmsi_api = {
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.configure = ss_spi_qmsi_configure,
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.slave_select = ss_spi_qmsi_slave_select,
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.transceive = ss_spi_qmsi_transceive,
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};
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#ifdef CONFIG_SPI_CS_GPIO
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static struct device *gpio_cs_init(struct ss_spi_qmsi_config *config)
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{
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struct device *gpio;
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if (!config->cs_port)
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return NULL;
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gpio = device_get_binding(config->cs_port);
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if (!gpio)
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return NULL;
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gpio_pin_configure(gpio, config->cs_pin, GPIO_DIR_OUT);
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gpio_pin_write(gpio, config->cs_pin, 1);
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return gpio;
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}
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#endif
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static int ss_spi_qmsi_init(struct device *dev);
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#ifdef CONFIG_SPI_0
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static struct ss_spi_qmsi_config spi_qmsi_mst_0_config = {
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.spi = QM_SS_SPI_0,
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#ifdef CONFIG_SPI_CS_GPIO
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.cs_port = CONFIG_SPI_0_CS_GPIO_PORT,
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.cs_pin = CONFIG_SPI_0_CS_GPIO_PIN,
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#endif
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};
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static struct ss_spi_qmsi_runtime spi_qmsi_mst_0_runtime;
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DEVICE_INIT(ss_spi_master_0, CONFIG_SPI_0_NAME,
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ss_spi_qmsi_init, &spi_qmsi_mst_0_runtime, &spi_qmsi_mst_0_config,
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SECONDARY, CONFIG_SPI_INIT_PRIORITY);
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#endif /* CONFIG_SPI_0 */
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#ifdef CONFIG_SPI_1
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static struct ss_spi_qmsi_config spi_qmsi_mst_1_config = {
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.spi = QM_SS_SPI_1,
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#ifdef CONFIG_SPI_CS_GPIO
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.cs_port = CONFIG_SPI_1_CS_GPIO_PORT,
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.cs_pin = CONFIG_SPI_1_CS_GPIO_PIN,
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#endif
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};
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static struct ss_spi_qmsi_runtime spi_qmsi_mst_1_runtime;
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DEVICE_INIT(ss_spi_master_1, CONFIG_SPI_1_NAME,
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ss_spi_qmsi_init, &spi_qmsi_mst_1_runtime, &spi_qmsi_mst_1_config,
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SECONDARY, CONFIG_SPI_INIT_PRIORITY);
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#endif /* CONFIG_SPI_1 */
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static void ss_spi_err_isr(void *arg)
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{
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struct device *dev = arg;
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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if (spi_config->spi == QM_SS_SPI_0) {
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qm_ss_spi_0_err_isr(NULL);
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} else {
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qm_ss_spi_1_err_isr(NULL);
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}
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}
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static void ss_spi_rx_isr(void *arg)
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{
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struct device *dev = arg;
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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if (spi_config->spi == QM_SS_SPI_0) {
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qm_ss_spi_0_rx_isr(NULL);
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} else {
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qm_ss_spi_1_rx_isr(NULL);
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}
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}
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static void ss_spi_tx_isr(void *arg)
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{
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struct device *dev = arg;
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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if (spi_config->spi == QM_SS_SPI_0) {
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qm_ss_spi_0_tx_isr(NULL);
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} else {
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qm_ss_spi_1_tx_isr(NULL);
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}
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}
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static int ss_spi_qmsi_init(struct device *dev)
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{
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struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
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struct ss_spi_qmsi_runtime *context = dev->driver_data;
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uint32_t *scss_intmask = NULL;
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switch (spi_config->spi) {
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#ifdef CONFIG_SPI_0
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case QM_SS_SPI_0:
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IRQ_CONNECT(IRQ_SPI0_ERR_INT, CONFIG_SPI_0_IRQ_PRI,
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ss_spi_err_isr, DEVICE_GET(ss_spi_master_0), 0);
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irq_enable(IRQ_SPI0_ERR_INT);
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IRQ_CONNECT(IRQ_SPI0_RX_AVAIL, CONFIG_SPI_0_IRQ_PRI,
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ss_spi_rx_isr, DEVICE_GET(ss_spi_master_0), 0);
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irq_enable(IRQ_SPI0_RX_AVAIL);
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IRQ_CONNECT(IRQ_SPI0_TX_REQ, CONFIG_SPI_0_IRQ_PRI,
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ss_spi_tx_isr, DEVICE_GET(ss_spi_master_0), 0);
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irq_enable(IRQ_SPI0_TX_REQ);
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ss_clk_spi_enable(0);
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/* Route SPI interrupts to Sensor Subsystem */
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scss_intmask = (uint32_t *)&QM_SCSS_INT->int_ss_spi_0;
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*scss_intmask &= ~BIT(8);
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scss_intmask++;
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*scss_intmask &= ~BIT(8);
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scss_intmask++;
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*scss_intmask &= ~BIT(8);
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break;
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#endif /* CONFIG_SPI_0 */
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#ifdef CONFIG_SPI_1
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case QM_SS_SPI_1:
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IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_1_IRQ_PRI,
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ss_spi_err_isr, DEVICE_GET(ss_spi_master_1), 0);
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irq_enable(IRQ_SPI1_ERR_INT);
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IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_1_IRQ_PRI,
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ss_spi_rx_isr, DEVICE_GET(ss_spi_master_1), 0);
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irq_enable(IRQ_SPI1_RX_AVAIL);
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IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_1_IRQ_PRI,
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ss_spi_tx_isr, DEVICE_GET(ss_spi_master_1), 0);
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irq_enable(IRQ_SPI1_TX_REQ);
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ss_clk_spi_enable(1);
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/* Route SPI interrupts to Sensor Subsystem */
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scss_intmask = (uint32_t *)&QM_SCSS_INT->int_ss_spi_1;
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*scss_intmask &= ~BIT(8);
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scss_intmask++;
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*scss_intmask &= ~BIT(8);
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scss_intmask++;
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*scss_intmask &= ~BIT(8);
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break;
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#endif /* CONFIG_SPI_1 */
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default:
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return -EIO;
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}
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#ifdef CONFIG_SPI_CS_GPIO
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context->gpio_cs = gpio_cs_init(spi_config);
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#endif
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device_sync_call_init(&context->sync);
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nano_sem_init(&context->sem);
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nano_sem_give(&context->sem);
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dev->driver_api = &ss_spi_qmsi_api;
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return 0;
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}
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