208 lines
4.1 KiB
Plaintext
208 lines
4.1 KiB
Plaintext
/*
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* Copyright (c) 2017 Piotr Mienkowski
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* Copyright (c) 2017 Justin Watson
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <atmel/same70_mem.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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};
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};
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flash0: flash@400000 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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reg = <0x00400000 DT_FLASH_SIZE>;
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};
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sram0: memory@20400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20400000 DT_SRAM_SIZE>;
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};
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soc {
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i2c0: i2c@40018000 {
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compatible = "atmel,sam-i2c-twihs";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40018000 0x12B>;
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interrupts = <19 0>;
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peripheral-id = <19>;
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label = "I2C_0";
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status = "disabled";
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};
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i2c1: i2c@4001C000 {
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compatible = "atmel,sam-i2c-twihs";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4001C000 0x12B>;
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interrupts = <20 0>;
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peripheral-id = <20>;
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label = "I2C_1";
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status = "disabled";
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};
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i2c2: i2c@40060000 {
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compatible = "atmel,sam-i2c-twihs";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40060000 0x12B>;
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interrupts = <41 0>;
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peripheral-id = <41>;
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label = "I2C_2";
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status = "disabled";
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};
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uart0: uart@400E0800 {
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compatible = "atmel,sam-uart";
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reg = <0x400E0800 0x100>;
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interrupts = <7 1>;
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peripheral-id = <7>;
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status = "disabled";
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label = "UART_0";
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};
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uart1: uart@400E0A00 {
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compatible = "atmel,sam-uart";
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reg = <0x400E0A00 0x100>;
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interrupts = <8 1>;
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peripheral-id = <8>;
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status = "disabled";
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label = "UART_1";
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};
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uart2: uart@400E1A00 {
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compatible = "atmel,sam-uart";
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reg = <0x400E1A00 0x100>;
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interrupts = <44 1>;
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peripheral-id = <44>;
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status = "disabled";
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label = "UART_2";
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};
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uart3: uart@400E1C00 {
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compatible = "atmel,sam-uart";
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reg = <0x400E1C00 0x100>;
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interrupts = <45 1>;
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peripheral-id = <45>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: uart@400E1E00 {
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compatible = "atmel,sam-uart";
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reg = <0x400E1E00 0x100>;
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interrupts = <46 1>;
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peripheral-id = <46>;
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status = "disabled";
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label = "UART_4";
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};
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usart0: usart@40024000 {
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compatible = "atmel,sam-usart";
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reg = <0x40024000 0x100>;
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interrupts = <13 0>;
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peripheral-id = <13>;
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status = "disabled";
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label = "USART_0";
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};
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usart1: usart@40028000 {
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compatible = "atmel,sam-usart";
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reg = <0x40028000 0x100>;
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interrupts = <14 0>;
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peripheral-id = <14>;
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status = "disabled";
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label = "USART_1";
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};
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usart2: usart@4002C000 {
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compatible = "atmel,sam-usart";
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reg = <0x4002C000 0x100>;
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interrupts = <15 0>;
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peripheral-id = <15>;
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status = "disabled";
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label = "USART_2";
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};
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adc0: adc@4003C000 {
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compatible = "atmel,sam-afec";
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reg = <0x4003C000 0x100>;
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interrupts = <29 0>;
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peripheral-id = <29>;
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status = "disabled";
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label = "ADC_0";
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};
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adc1: adc@40064000 {
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compatible = "atmel,sam-afec";
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reg = <0x40064000 0x100>;
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interrupts = <40 0>;
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peripheral-id = <40>;
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status = "disabled";
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label = "ADC_1";
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};
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porta: gpio@400E0E00 {
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compatible = "atmel,sam-gpio";
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reg = <0x400E0E00 0x190>;
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interrupts = <10 1>;
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peripheral-id = <10>;
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label = "PORTA";
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};
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portb: gpio@400E1000 {
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compatible = "atmel,sam-gpio";
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reg = <0x400E1000 0x190>;
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interrupts = <11 1>;
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peripheral-id = <11>;
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label = "PORTB";
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};
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portc: gpio@400E1200 {
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compatible = "atmel,sam-gpio";
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reg = <0x400E1200 0x190>;
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interrupts = <12 1>;
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peripheral-id = <12>;
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label = "PORTC";
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};
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portd: gpio@400E1400 {
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compatible = "atmel,sam-gpio";
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reg = <0x400E1400 0x190>;
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interrupts = <16 1>;
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peripheral-id = <16>;
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label = "PORTD";
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};
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porte: gpio@400E1600 {
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compatible = "atmel,sam-gpio";
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reg = <0x400E1600 0x190>;
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interrupts = <17 1>;
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peripheral-id = <17>;
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label = "PORTE";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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