zephyr/dts/arm/atmel/same70.dtsi

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/*
* Copyright (c) 2017 Piotr Mienkowski
* Copyright (c) 2017 Justin Watson
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <atmel/same70_mem.h>
#include <dt-bindings/i2c/i2c.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
reg = <0>;
};
};
flash0: flash@400000 {
compatible = "soc-nv-flash";
label = "FLASH_0";
reg = <0x00400000 DT_FLASH_SIZE>;
};
sram0: memory@20400000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20400000 DT_SRAM_SIZE>;
};
soc {
i2c0: i2c@40018000 {
compatible = "atmel,sam-i2c-twihs";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40018000 0x12B>;
interrupts = <19 0>;
peripheral-id = <19>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@4001C000 {
compatible = "atmel,sam-i2c-twihs";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4001C000 0x12B>;
interrupts = <20 0>;
peripheral-id = <20>;
label = "I2C_1";
status = "disabled";
};
i2c2: i2c@40060000 {
compatible = "atmel,sam-i2c-twihs";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40060000 0x12B>;
interrupts = <41 0>;
peripheral-id = <41>;
label = "I2C_2";
status = "disabled";
};
uart0: uart@400E0800 {
compatible = "atmel,sam-uart";
reg = <0x400E0800 0x100>;
interrupts = <7 1>;
peripheral-id = <7>;
status = "disabled";
label = "UART_0";
};
uart1: uart@400E0A00 {
compatible = "atmel,sam-uart";
reg = <0x400E0A00 0x100>;
interrupts = <8 1>;
peripheral-id = <8>;
status = "disabled";
label = "UART_1";
};
uart2: uart@400E1A00 {
compatible = "atmel,sam-uart";
reg = <0x400E1A00 0x100>;
interrupts = <44 1>;
peripheral-id = <44>;
status = "disabled";
label = "UART_2";
};
uart3: uart@400E1C00 {
compatible = "atmel,sam-uart";
reg = <0x400E1C00 0x100>;
interrupts = <45 1>;
peripheral-id = <45>;
status = "disabled";
label = "UART_3";
};
uart4: uart@400E1E00 {
compatible = "atmel,sam-uart";
reg = <0x400E1E00 0x100>;
interrupts = <46 1>;
peripheral-id = <46>;
status = "disabled";
label = "UART_4";
};
usart0: usart@40024000 {
compatible = "atmel,sam-usart";
reg = <0x40024000 0x100>;
interrupts = <13 0>;
peripheral-id = <13>;
status = "disabled";
label = "USART_0";
};
usart1: usart@40028000 {
compatible = "atmel,sam-usart";
reg = <0x40028000 0x100>;
interrupts = <14 0>;
peripheral-id = <14>;
status = "disabled";
label = "USART_1";
};
usart2: usart@4002C000 {
compatible = "atmel,sam-usart";
reg = <0x4002C000 0x100>;
interrupts = <15 0>;
peripheral-id = <15>;
status = "disabled";
label = "USART_2";
};
adc0: adc@4003C000 {
compatible = "atmel,sam-afec";
reg = <0x4003C000 0x100>;
interrupts = <29 0>;
peripheral-id = <29>;
status = "disabled";
label = "ADC_0";
};
adc1: adc@40064000 {
compatible = "atmel,sam-afec";
reg = <0x40064000 0x100>;
interrupts = <40 0>;
peripheral-id = <40>;
status = "disabled";
label = "ADC_1";
};
porta: gpio@400E0E00 {
compatible = "atmel,sam-gpio";
reg = <0x400E0E00 0x190>;
interrupts = <10 1>;
peripheral-id = <10>;
label = "PORTA";
};
portb: gpio@400E1000 {
compatible = "atmel,sam-gpio";
reg = <0x400E1000 0x190>;
interrupts = <11 1>;
peripheral-id = <11>;
label = "PORTB";
};
portc: gpio@400E1200 {
compatible = "atmel,sam-gpio";
reg = <0x400E1200 0x190>;
interrupts = <12 1>;
peripheral-id = <12>;
label = "PORTC";
};
portd: gpio@400E1400 {
compatible = "atmel,sam-gpio";
reg = <0x400E1400 0x190>;
interrupts = <16 1>;
peripheral-id = <16>;
label = "PORTD";
};
porte: gpio@400E1600 {
compatible = "atmel,sam-gpio";
reg = <0x400E1600 0x190>;
interrupts = <17 1>;
peripheral-id = <17>;
label = "PORTE";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};