157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* Copyright (c) 2017 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <watchdog.h>
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#define WDT_REGS ((Wdt *)CONFIG_WDT_SAM0_BASE_ADDRESS)
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struct wdt_sam0_dev_data {
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void (*cb)(struct device *dev);
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};
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static struct device DEVICE_NAME_GET(wdt_sam0);
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static void wdt_sam0_wait_synchronization(void)
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{
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while (WDT_REGS->STATUS.bit.SYNCBUSY) {
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}
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}
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static void wdt_sam0_isr(struct device *dev)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
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if (data->cb != NULL) {
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data->cb(dev);
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}
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}
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static void wdt_sam0_enable(struct device *dev)
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{
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WDT_REGS->CTRL.reg = WDT_CTRL_ENABLE;
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wdt_sam0_wait_synchronization();
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}
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static void wdt_sam0_disable(struct device *dev)
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{
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WDT_REGS->CTRL.reg = 0;
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wdt_sam0_wait_synchronization();
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}
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static int wdt_sam0_set_config(struct device *dev, struct wdt_config *config)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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WDT_CTRL_Type ctrl = WDT_REGS->CTRL;
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int divisor;
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/* As per wdt_esp32.c, the Zephyr watchdog API is modeled
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* after the Quark MCU where:
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*
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* timeout_ms = 2**(config->timeout + 11) / 1000
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*
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* The SAM0 is also power-of-two based with a 1 kHz clock, so
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* 2**14 / 1kHz ~= 2**29 / 32 MHz.
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*/
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divisor = config->timeout + WDT_CONFIG_PER_16K_Val - WDT_2_29_CYCLES;
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/* Limit to 16x so that 8x is available for early warning. */
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if (divisor < WDT_CONFIG_PER_16_Val) {
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return -EINVAL;
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} else if (divisor > WDT_CONFIG_PER_16K_Val) {
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return -EINVAL;
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}
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/* Disable the WDT to change the config. */
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wdt_sam0_disable(dev);
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switch (config->mode) {
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case WDT_MODE_RESET:
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WDT_REGS->INTENCLR.reg = WDT_INTENCLR_EW;
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wdt_sam0_wait_synchronization();
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break;
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case WDT_MODE_INTERRUPT_RESET:
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/* Fire the early warning earlier. */
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WDT_REGS->EWCTRL.bit.EWOFFSET = divisor - 1;
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wdt_sam0_wait_synchronization();
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/* Clear the pending interrupt, if any. */
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WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
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wdt_sam0_wait_synchronization();
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WDT_REGS->INTENSET.reg = WDT_INTENSET_EW;
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wdt_sam0_wait_synchronization();
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break;
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default:
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return -EINVAL;
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}
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WDT_REGS->CONFIG.bit.PER = divisor;
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wdt_sam0_wait_synchronization();
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data->cb = config->interrupt_fn;
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WDT_REGS->CTRL = ctrl;
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wdt_sam0_wait_synchronization();
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return 0;
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}
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static void wdt_sam0_get_config(struct device *dev, struct wdt_config *config)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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if (WDT_REGS->INTENSET.bit.EW) {
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config->mode = WDT_MODE_INTERRUPT_RESET;
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} else {
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config->mode = WDT_MODE_RESET;
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}
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config->timeout = WDT_REGS->CONFIG.bit.PER
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+ WDT_2_29_CYCLES - WDT_CONFIG_PER_16K_Val;
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config->interrupt_fn = data->cb;
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}
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static void wdt_sam0_reload(struct device *dev)
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{
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WDT_REGS->CLEAR.bit.CLEAR = WDT_CLEAR_CLEAR_KEY_Val;
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}
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static const struct wdt_driver_api wdt_sam0_api = {
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.enable = wdt_sam0_enable,
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.disable = wdt_sam0_disable,
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.get_config = wdt_sam0_get_config,
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.set_config = wdt_sam0_set_config,
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.reload = wdt_sam0_reload,
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};
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static int wdt_sam0_init(struct device *dev)
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{
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/* Enable APB clock */
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PM->APBAMASK.bit.WDT_ = 1;
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/* Connect to GCLK2 (~1 kHz) */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
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| GCLK_CLKCTRL_GEN_GCLK2
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| GCLK_CLKCTRL_CLKEN;
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IRQ_CONNECT(CONFIG_WDT_SAM0_IRQ,
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CONFIG_WDT_SAM0_IRQ_PRIORITY, wdt_sam0_isr,
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DEVICE_GET(wdt_sam0), 0);
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irq_enable(CONFIG_WDT_SAM0_IRQ);
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return 0;
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}
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static struct wdt_sam0_dev_data wdt_sam0_data;
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DEVICE_AND_API_INIT(wdt_sam0, CONFIG_WDT_SAM0_LABEL, wdt_sam0_init,
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&wdt_sam0_data, NULL, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sam0_api);
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